Ex Parte Shah et al

Patent Trial and Appeal BoardNov 29, 2012

11171862 (P.T.A.B. Nov. 29, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/171,862 06/30/2005 Shrikant M. Shah P21824(4010) 4676 50889 7590 11/30/2012 SCHUBERT LAW GROUP PLLC c/o CPA Global P.O. BOX 52050 MINNEAPOLIS, MN 55402 EXAMINER HUYNH, KIM T ART UNIT PAPER NUMBER 2111 MAIL DATE DELIVERY MODE 11/30/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte SHRIKANT M. SHAH, PETER C. BRINK, AND PETER MUNGUIA Appeal 2010-006817 Application 11/171,8621 Technology Center 2100 ____________ Before THU A. DANG, JAMES R. HUGHES, and GREGORY J. GONSALVES, Administrative Patent Judges. HUGHES, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1-5, 7-16, and 18-25, which are all the claims remaining in the application. Claims 6, 17, and 26-29 were cancelled during prosecution. We have jurisdiction under 35 U.S.C. § 6(b). 1 Application filed on June 30, 2005. The Real Party in Interest is Intel Corporation. (App. Br. 3.) Appeal 2010-006817 Application 11/171,862 2 We affirm-in-part. Appellants’ Invention Appellants’ invention is in the field of interrupt processing. More particularly, the invention relates to methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing the interrupts indicated by the transactions. Further embodiments provide backward compatibility for double word MSIs. (Spec. 1, ¶ [0001].)2 Representative Claim Independent claim 1, reproduced below with the key disputed limitations emphasized, further illustrates the invention: 1. A method comprising: receiving, at a processor, a message signal interrupt initiated by a device, wherein the message signal interrupt comprises attributes, a vector, and data to service an interrupt; storing, by the processor, the data in a buffer, wherein a latency associated with retrieval of the data from the buffer by the processor is lower than a latency associated with retrieval of the data from the device; and retrieving, by the processor, the data from the buffer to service the interrupt. Rejections on Appeal 1. The Examiner rejects claims 1-5, 7-16, 18-23, and 25 under 35 U.S.C. § 102(b) as being anticipated by Lai (U.S. 2001/0032287 A1, published Oct. 18, 2001). 2 We refer to Appellants’ Specification (“Spec.”); Reply Brief (“Reply Br.”) filed Jan. 12, 2010; and Appeal Brief (“Br.”) filed Jan. 9, 2009. We also refer to the Examiner’s Answer (“Ans.”) mailed Nov. 12, 2009. Appeal 2010-006817 Application 11/171,862 3 2. The Examiner rejects claim 24 under 35 U.S.C. § 103(a) as being unpatentable over Lai and Burshtein (U.S. 5,771,374, issued June 23, 1998). ISSUE Based upon our review of the administrative record, Appellants’ contentions, and the Examiner’s findings and conclusions, we have determined that the following issue is dispositive in this appeal: Under § 102, did the Examiner err in finding that Lai discloses or describes “storing, by the processor, the data in a buffer, wherein a latency associated with retrieval of the data from the buffer by the processor is lower than a latency associated with retrieval of the data from the device” (emphasis added), within the meaning of independent claims 1, 14, and 21? ANALYSIS Independent Claim 1 Appellants contend that Lai fails to describe, expressly or inherently, storing, by the processor, the data in a buffer. (App. Br. 8.) We agree for essentially the same reasons argued by Appellants. Under § 102, the elements must be arranged as required by the claim.3 We find that claim 1 requires that the data received by the processor is stored in the buffer. The cited portion of Lai discloses outputting an interrupt signal to the central processing unit right after the data to be processed is completely written to the system memory. (Ans. 10; Lai ¶ [0013].) Therefore, Lai appears to disclose or describe storing the data prior 3 Net MoneyIN, Inc. v. Verisign, Inc., 545 F.3d 1359 (Fed. Cir. 2008). Appeal 2010-006817 Application 11/171,862 4 to transmitting the interrupt, rather than the message signal interrupt including data to service an interrupt as required by the claim. Based on this record, we conclude that the Examiner erred in finding that Lai discloses or describes storing, by the processor, the data in a buffer, as recited in claim 1. Accordingly, we reverse the Examiner’s rejection of claim 1 and associated dependent claims 2-5 and 7-13. Independent Claims 14 and 21 Apparatus claims 14 and 21 recite limitations that are commensurate with the disputed limitations recited in claim 1. (See App. Br. 8-11.) We note that a portion of the disputed limitations, “the message signal interrupt comprises attributes, a vector, and data to service and interrupt, and to store the data in a buffer,” is essentially a statement of intended use or purpose of the processor’s interrupt handler (claim 14) and the chipset’s interrupt queue (claim 21). The intended use does not change the structure of the processor and chipset and, in this instance, does not further limit the scope of the claims. See Boehringer Ingelheim Vetmedica, Inc. v. Schering- Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003) (a statement of intended use “usually will not limit the scope of the claim because such statements usually do no more than define a context in which the invention operates”). We agree with and adopt the Examiner’s findings with respect to the structural elements of claims 14 and 21. (Ans. 3-4, 7.) We will not give patentable weight to the statements of intended use recited in claims 14 and 21. On the record before us, we conclude that Appellants have not shown the Examiner erred in rejecting independent claims 14 and 21 for the reasons Appeal 2010-006817 Application 11/171,862 5 discussed supra. Accordingly, we affirm the Examiner’s anticipation rejection of independent claims 14 and 21 and associated dependent claims 15, 16, 18-20, 22, 23, and 25. Claim 24 As noted above, claim 24 stands rejected as unpatentable under § 103. Appellants did not argue for the patentability of dependent claim 24 with specificity. (App. Br. 13.) Accordingly, we affirm the Examiner’s rejection of claim 24 for the same reasons discussed supra regarding independent claim 21. CONCLUSION OF LAW Appellants have shown that the Examiner erred in rejecting claims 1-5 and 7-13 under 35 U.S.C. § 102(b). Appellants have not shown that the Examiner erred in rejecting claims 14-16, 18-23, and 25 under 35 U.S.C. § 102(b). Appellants have not shown that the Examiner erred in rejecting claim 24 under 35 U.S.C. § 103. DECISION We reverse the Examiner’s rejection of claims 1-5, and 7-13 under 35 U.S.C. § 102(b). We affirm the Examiner’s rejection of claims 14-16, 18-23, and 25 under 35 U.S.C. § 102(b). We affirm the Examiner’s rejection of claim 24 under 35 U.S.C. § 103(a). Appeal 2010-006817 Application 11/171,862 6 AFFIRMED-IN-PART peb