Ex Parte Sankaran

Patent Trials and Appeals Board

Mar 21, 2019

12131563 - (D) (P.T.A.B. Mar. 21, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/131,563 06/02/2008
23494 7590 03/25/2019
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Jagadeesh Sankaran
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-63939 6069
EXAMINER
PARK,HYUND
ART UNIT PAPER NUMBER
2865
NOTIFICATION DATE DELIVERY MODE
03/25/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JAGADEESH SANKARAN
Appeal2017-006472
Application 12/131,563 1
Technology Center 2800
Before BRADLEY R. GARRIS, ADRIENE LEPIANE HANLON, and
KRISTINA M. KALAN, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellant filed an appeal under 35 U.S.C. § 134(a) from an
Examiner's decision finally rejecting claims 1--4, 6, and 7. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Independent claims 1 and 4 are reproduced below from the Claims
Appendix to the Appeal Brief. The limitations at issue are italicized.
1 The real party in interest is said to be Texas Instruments Incorporated.
Appeal Brief dated September 20, 2016 ("App. Br."), at 3.
Appeal2017-006472
Application 12/131,563
1. An execution benchmarking apparatus for a
multiprocessor system comprising:
a plurality of data processing units, each data processing
unit including at least one functional unit, each data processing
unit operable to perform data processing operations in response
to program instructions synchronously with a corresponding
clock, each data processing unit including a benchmark counter,
said benchmark counter operable to count clock cycles of said
corresponding digital processing unit when said corresponding
data processing unit is operating, each data processing unit
operable to
App. Br. 19.
begin data processing operations on a benchmark
program on said at least one functional unit on said data
processing unit and reset said benchmark counter upon
detection of a start command,
increment said corresponding benchmark counter
synchronously with each clock cycle of said
corresponding clock following said detection of said start
command,
stopping data processing operations on the
benchmark program on said at least one functional unit
on said data processing unit upon detection of a stop
command,
not incrementing said benchmark counter
synchronously with each clock cycle of said
corresponding clock following said detection of said stop
command, said benchmark counter thereby storing a
number of clocks consumed by said data processing unit
from said start command to said stop command, and
permitting said corresponding benchmark counter
to be read when stopped.
4. A method of benchmarking an individual processor in a
multiple processor system comprising the steps of:
disposing a benchmark counter on each data processor;
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loading a benchmark program on each data processor;
transmitting a start command to a data processor;
upon detection of a start command at a data processor
starting data processing operations on said data processor by
executing the benchmark program on at least one functional
unit of said data processor synchronously with a corresponding
data processor clock and resetting said corresponding
benchmark counter,
following said detection of said start command
incrementing said corresponding benchmark counter
synchronously with each clock cycle of said corresponding data
processor clock;
transmitting a stop command to said data processor;
upon detection of a stop command at said data processor
stopping data processing operations on said at least one
functional unit of said data processing unit executing the
benchmark program;
following said detection of said stop command stopping
incrementing said corresponding benchmark counter, said
benchmark counter thereby storing a number of clocks
consumed by said corresponding data processor from said start
command to said stop command; and
reading a value from said benchmark counter.
App. Br. 20-21.
The claims on appeal stand rejected as follows:
(1) claims 1--4, 6, and 7 under 35 U.S.C. § 112, first paragraph, as
failing to comply with the written description requirement; and
(2) claims 1--4, 6, and 7 under 35 U.S.C. § 102(b) as anticipated by
Chapple. 2
2 US 6,519,310 B2, issued February 11, 2003 ("Chapple").
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A Decision on Appeal was entered by the Board in the instant
Application on November 4, 2014, affirming the Examiner's decision to
reject claims 1-7 under 35 U.S.C. § 102(b) as anticipated by Chapple.
According to the Examiner, the claims currently on appeal in this second
appeal are substantially identical to the claims in the first appeal "except for
the addition of the new limitations involving the 'at least one functional
unit."' Ans. 3; 3 see also Reply Br. 74 (contending that "[a]s now recited in
claims 1 and 4, data processing occurs in the 'at least one functional unit"').
According to the Appellant, "the current language that data processing
occurs in 'at least one functional unit of said data processor' was added to
preclude an interpretation that the counting of the benchmark counters
constitutes data processing." Reply Br. 5.
B. DISCUSSION
1. Rejection (1)
The Examiner finds that the following limitations recited in claims 1
and 4 are not supported by the original disclosure (Final Act. 2-3 5):
each data processing unit operable to begin data processing
operations on a benchmark program on said at least one
functional unit on said data processing unit and reset said
benchmark counter upon detection of a start command ...
stopping data processing operations on the benchmark program
on said at least one functional unit on said data processing unit
upon detection of a stop command ....
App. Br. 19 (emphasis added); see also Final Act. 2-3.
executing the benchmark program on at least one functional
unit of said data processor synchronously with a corresponding
3 Examiner's Answer dated January 13, 2017.
4 Reply Brief dated March 8, 2017.
5 Final Office Action dated April 27, 2016.
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Application 12/131,563
data processor clock and resetting said corresponding
benchmark counter ... upon detection of a stop command at
said data processor stopping data processing operations on said
at least one functional unit of said data processing unit
executing the benchmark program ....
App. Br. 20 (emphasis added); see also Final Act. 3. 6
The Examiner finds that "while the original disclosure discloses
beginning ( and ending) the data processing operations on a benchmark
program on a processor in general terms, it does not disclose beginning ( and
ending) the data processing operations on a benchmark program on ANY
specific components within the processor, including the claimedfunctional
units." Ans. 6 (italics added); see also Final Act. 3 (finding that "the
Specification does not specifically disclose performing the benchmark
program on any specific internal component of the data processing unit
(namely the functional unit as recited in Claims 1 and 4)" ( emphasis
omitted)).
To satisfy the written description requirement, a patent applicant must
"convey with reasonable clarity to those skilled in the art that, as of the filing
date sought, he or she was in possession of the invention." Vas-Cath Inc. v.
Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991) (emphasis omitted).
"The written description requirement does not require the applicant 'to
describe exactly the subject matter claimed, [instead] the description must
6 The Examiner misquotes a portion of claim 4 on page 3 of the Final Office
Action (i.e., "said benchmark counter thereby storing a number of clocks
consumed by said corresponding at least one functional unit of said data
processor"). Final Act. 3. That limitation is not at issue in the written
description rejection on appeal. Nonetheless, the Appellant contends that
the recitation "'of said at least one functional unit'" was deleted in an
amendment filed on November 11, 2015. App. Br. 9.
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clearly allow persons of ordinary skill in the art to recognize that [he or she]
invented what is claimed." Union Oil Co. of Cal. v. Atlantic Riclifield Co.,
208 F.3d 989,997 (Fed. Cir. 2000) (quoting In re Gosteli, 872 F.2d 1008,
1012 (Fed. Cir. 1989)).
A disclosure may provide either express or inherent support for the
claimed invention. Tronzo v. Biomet, Inc., 156 F.3d 1154, 1159 (Fed. Cir.
1998). "In order for a disclosure to be inherent, however, the missing
descriptive matter must necessarily be present in the ... application's
specification such that one skilled in the art would recognize such a
disclosure." Id.; see also Hansgirg v. Kemmer, 102 F.2d 212,214
(CCP A 1939) ("Inherency ... may not be established by probabilities or
possibilities.").
The instant Application was filed with Figures 1-7. The Appellant
describes Figures 1---6 as "prior art." Spec. 4, 1. 20-5, 1. 10; Figs. 1---6.
Figure 7 is said to "illustrate[] the process of [the Appellant's] invention in
benchmark mode." Spec. 21, 11. 14--15. Original claim 5 recites the step of
operating a data processor on a benchmark program. Spec. 24. The original
disclosure, however, does not expressly describe "[a] benchmark program on
said at least one functional unit on said data processing unit" as recited in
claim 1 or "executing the benchmark program on at least one functional unit
of said data processor" as recited in claim 4. App. Br. 19, 20 ( emphasis
added).
The Appellant, nonetheless, relies on various portions of the
Specification in an attempt to establish that the original disclosure inherently
describes the claim language at issue. See App. Br. 10-11 (citing page 21,
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lines 15-18; page 9, lines 4--12; page 12, lines 8-10; and page 10, lines 15-
20 of the Specification).
First, the Appellant contends that "[t]he original application discloses
that all data processing performed by the data processing unit is performed
by the functional units." App. Br. 10 (emphasis added). The Appellant
directs us to page 21, lines 15-18 of the Specification, which states that
"[e]ach processor [in the Appellant's invention] is loaded with appropriate
software for the benchmark. This will generally be an example of software
of the type that will be used in the operating system." The Appellant,
however, does not direct us to any portion of the original disclosure stating
that "all data processing performed by the data processing unit is performed
by the functional units." App. Br. 10 (emphasis added).
Next, the Appellant argues that "[i]t is known in the art that such
software [i.e., the software for the benchmark] consists of a sequence of
program instructions." App. Br. 10. The Appellant directs us to page 9,
lines 4--12 of the Specification, describing the details of the prior art digital
signal processor integrated circuit illustrated in Figure 2, which is said to be
"suitable but not essential for use in this invention." Spec. 7, 11. 3-5
(emphasis added). According to the Appellant, "[t]his portion of the
application states that data processing occurs in the two data paths 20 and
30, each of which includes 4 functional units. This portion of the application
also states that each functional unit 'is controlled by' an instruction."7 App.
7 See Spec. 9, 11. 8-10 ( disclosing that processing occurs in each of two data
paths 20 and 30, and each data path has four corresponding functional units
(L, S, M, and D)); Spec. 9, 1. 12 (disclosing that "[e]ach functional unit is
controlled by a 32-bit instruction"); see also Spec. 12, 11. 6-10 (disclosing
that "prior art" Figure 4 "illustrates an example of the instruction coding of
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Br. 10. The Appellant argues that "this disclosure is the same as a disclosure
that each functional unit performs data processing according to this
instruction." App. Br. 10-11 (emphasis added).
Finally, the Appellant directs us to page 10, lines 15-20 of the
Specification, describing the pipeline stages (prior art Figure 3) of digital
signal processor core 110 (prior art Figure 1 ). 8 App. Br. 11; Spec. 9, 11. 16-
17. The Appellant argues that "[t]his portion of the application teaches that
instructions are assigned to 'appropriate' functional units which execute
these instructions." App. Br. 11; see also Spec. 10, 11. 15-16 (disclosing that
during an instruction dispatch (DP) phase 322 in decode group 320,
"instructions in an execute packet are assigned to the appropriate functional
units").
Based on the foregoing, the Appellant argues that "[t]he application
thus teaches that data processing operations of instructions are performed by
the functional unit." App. Br. 11. The Appellant argues that "this teaching
of performing data processing operations in the functional units applies to
any instructions of a benchmark program." App. Br. 11. Therefore, the
Appellant argues that "the application teaches the limitation 'data processing
operations on a benchmark program on said at least one functional unit on
said data processing unit' of claim 1 and the limitation 'executing the
instructions used by digital signal processor core 110 [(illustrated in "prior
art" Figure 1 ); e Jach instruction ... controls the operation of one of the eight
functional units").
8 The Appellant discloses that the pipeline stages are divided into three
groups: fetch group 310; decode group 320; and execute group 330. Spec.
9, 11. 17-19.
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benchmark program on at least one functional unit of said data processor' of
claim 4." App. Br. 11.
The Appellant's arguments are not persuasive of reversible error.
Although the Application, as originally filed, discloses some examples of
data processing performed by the functional unit(s) of the data processing
unit, the Application, as originally filed, does not disclose that all data
processing performed by the data processing unit, including the Appellant's
benchmark program, is performed by the functional unit(s). See App. Br. 10
(arguing that "[t]he original application discloses that all data processing
performed by the data processing unit is performed by the functional units"
(emphasis added)). Moreover, the Appellant does not direct us to any
portion of the original disclosure indicating that, at the time of filing, the
Appellant contemplated performing the instructions of the benchmark
program on the functional unit(s) of the data processing unit.
Thus, on this record, it is not reasonably clear that, at the time the
instant Application was filed, the Appellant was in possession of the
following claim limitations:
• "begin data processing operations on a benchmark program
on said at least one functional unit on said data processing unit"
( claim 1 ),
• "stopping data processing operations on the benchmark
program on said at least one functional unit on said data
processing unit" ( claim 1 ),
• "starting data processing operations on said data processor by
executing the benchmark program on at least one functional
unit of said data processor" (claim 4), and
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• "stopping data processing operations on said at least one
functional unit of said data processing unit9 executing the
benchmark program" ( claim 4).
App. Br. 19, 20 (emphasis added). For that reason, a preponderance of the
evidence of record supports the Examiner's finding that the original
disclosure does not provide written description support for the claim
language identified above.
The Examiner also finds that the following limitation, recited in
claim 1, is not supported by the original disclosure: "[each data processing
unit operable to] begin data processing operations on a benchmark program
on said at least one functional unit on said data processing unit and reset
said benchmark counter upon detection of a start command." App. Br. 19
( emphasis added); see also Final Act. 4. Referring to Figure 7, the Examiner
finds that Start Command 701 is followed by Reset Counter 702 which is
followed by Start Processor and Counter 703. Final Act. 4; Fig. 7. The
Examiner finds that the original disclosure "does not disclose first beginning
the data processing operations followed by resetting the counter, as claimed."
Final Act. 4 ( emphasis added).
The Appellant argues:
[T]his limitation of claim 1 does not require any ordering
between resetting the counter and beginning data processing.
As a matter of claim interpretation, the order of events listed in
the claim does not require the events occur in that order. The
only limitation within claim 1 is that each of these events
occurs "upon detection of a start command." Figure 7 and the
accompanying text teaches that each of these events occur
9 In claim 4, "said data processing unit" lacks antecedent basis. Thus, we
understand "said data processing unit" to be a "data processor" in claim 4.
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following (upon detection of) the start command. Thus this is
taught in the application.
App. Br. 11-12.
The Appellant's argument is supported by the record. "Unless the
steps of a method actually recite an order, the steps are not ordinarily
construed to require one." Interactive Gift Express, Inc. v. Compuserve Inc.,
231 F.3d 859, 875 (Fed. Cir. 2000). In contrast to claim 4, claim 1 does not
recite a method. 1° Claim 1 recites an apparatus comprising, inter alia, "each
data processing unit operable to begin data processing operations on a
benchmark program ... and reset said benchmark counter upon detection of
a start command." App. Br. 19 (emphasis added). Claim 1 does not recite
that those functions must be performed sequentially. That is, claim 1 does
not recite that data processing operations must begin before the benchmark
counter is reset. Thus, we interpret claim 1 as merely reciting that each data
processing unit is capable of performing the two recited functions, in no
particular order, "upon detection of a start command." App. Br. 19.
Figure 7 describes starting the processor (703) and resetting the
counter (702) when a start command is received. Spec. 21, 1. 26-22, 1. 2.
Therefore, we find that the original disclosure provides written description
support for the following limitation recited in claim 1: "each data
processing unit operable to begin data processing operations on a
10 Notably, the Examiner did not find that the following limitation recited in
method claim 4 is not supported by the original disclosure: "upon detection
of a start command at a data processor starting data processing operations
on said data processor by executing the benchmark program ... and
resetting said corresponding benchmark counter." App. Br. 20 (emphasis
added).
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benchmark program ... and reset said benchmark counter upon detection of
a start command." App. Br. 19 ( emphasis added).
That being said, for the reasons discussed above, the following
limitations are not supported by the original disclosure:
• "begin data processing operations on a benchmark program
on said at least one functional unit on said data processing unit"
( claim 1 ),
• "stopping data processing operations on the benchmark
program on said at least one functional unit on said data
processing unit" ( claim 1 ),
• "starting data processing operations on said data processor by
executing the benchmark program on at least one functional
unit of said data processor" (claim 4), and
• "stopping data processing operations on said at least one
functional unit of said data processing unit executing the
benchmark program" ( claim 4).
App. Br. 19, 20 ( emphasis added). Therefore, the rejection of claims 1--4, 6,
and 7 under 35 U.S.C. § 112, first paragraph, as failing to comply with the
written description requirement, is sustained.
2. Rejection (2)
The Examiner finds Chapple discloses an execution benchmarking
system and a corresponding method. Final Act. 4. The Examiner finds
Chapple' s system comprises a plurality of counter blocks ( corresponding to
the claimed plurality of data processing units), wherein each counter block
includes at least one functional unit and is operable to perform data
processing operations synchronously with a corresponding clock. Final
Act. 5. The Examiner finds that each counter block (i.e., data processing
unit) includes a performance counter ( corresponding to the claimed
benchmark counter) that is operable to count clock cycles of the
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corresponding counter block when the corresponding counter block is
operating. 11 Final Act. 5.
The Examiner finds that command triggers 102; command, status, &
event registers & control logic 105; registers 106, multiplexers, and other
logics within the counter blocks correspond to the claimed functional units.
Final Act. 5, 1 O; Ans. 8. The Examiner finds that each counter block is
operable to begin data processing operations on a benchmark program on at
least one functional unit on the counter block and reset the performance
counter following detection of a start command. Final Act. 5 ( citing
Chapple, col. 5, 11. 9-12). The Examiner finds that upon detection of a stop
command, data processing operations on the benchmark program on at least
one functional unit on the counter block stop. Final Act. 7 ( citing Chapple,
col. 4, 11. 1-3, 59-61; id. at col. 6, 11. 32-38; id. at 7, 11. 1-10); see also Final
Act. 13 (citing Chapple, col. 4, 11. 59-61; id. at col. 6, 11. 35-38).
The Appellant argues that the portions of Chapple relied on by the
Examiner fail to mention "'stopping data processing operations'" as recited
in claims 1 and 4. App. Br. 15. Although Chapple teaches stopping the
performance counters, the Appellant argues that Chapple
include[ s] no teaching regarding the limitation "stopping data
processing operations on said data processing unit upon
detection of a stop command" of claim 1 or the limitation of
"upon detection of a stop command at said data processor
11 Claim 1 recites "said benchmark counter operable to count clock cycles of
said corresponding digital processing unit when said corresponding data
processing unit is operating." App. Br. 19 (emphasis added). The phrase
"said corresponding digital processing unit" lacks antecedent basis. Thus,
we understand the "digital processing unit" recited in claim 1 to be a "data
processing unit."
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stopping data processing operations on said data processing
unit' of claim 4."
App. Br. 15. In that regard, the Appellant argues that "[b]oth claims 1 and 4
recites that the data processing operations occur in the functional units and
do not recite that the benchmark counters perform the recited data
processing operations." App. Br. 15 (emphasis added).
In response, the Examiner finds that Chapple discloses that "'if the
command is a Stop command, then the associated counter does not count'
(Col. 4, lines 59-61; Col. 6, lines 35-38)." Ans. 12 (emphasis omitted); see
also Final Act. 13. Moreover, the Examiner finds that "counting events is
[a] data processing operation. As such, stopping the counter, stops counting,
or stops data processing operations." Ans. 12 (emphasis added); see also
Final Act. 13.
Claim 1 recites, in relevant part, "stopping data processing operations
on the benchmark program on said at least one functional unit on said data
processing unit upon detection of a stop command." App. Br. 19 (emphasis
added). Similarly, claim 4 recites, in relevant part, "upon detection of a stop
command at said data processor stopping data processing operations on said
at least one functional unit of said data processing unit executing the
benchmark program." App. Br. 20 (emphasis added).
A reference is anticipatory under 35 U.S.C. § 102(b) when it discloses
each and every element of the claimed invention, arranged or combined in
the same way as in the claim. In re Gleave, 560 F.3d 1331, 1334 (Fed.
Cir. 2009). The Examiner bears the initial burden of presenting a prima
facie case of anticipation. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir.
1992).
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In this case, the Examiner relies on several portions of Chapple to
establish anticipation. See Final Act. 7 ( citing Chapple, col. 4, 11. 59---61; id.
at col. 6, 11. 32-3 8; id. at 7, 11. 1-1 O); 12 Final Act. 13 ( citing Chapple, col. 4,
11. 59---61; id. at col. 6, 11. 35-38).
The first portion of Chapple relied on by the Examiner states, "If the
command is a Stop command, then the associated counter does not count. If
the command is a Start command, then the associated counter begins
counting." Chapple, col. 4, 11. 59---62 ( emphasis added).
The Appellant argues that "[ t ]his portion of Chapple teach[ es]
counting starts and stops but fails to teach that the benchmark program starts
and stops correspondingly [as] required by the language of claims 1 and 4."
Reply Br. 7. Indeed, this portion of Chapple does not describe stopping data
processing operations on the benchmark program as recited in claim 1 or
stopping data processing operations on the functional unit(s) executing the
benchmark program as recited in claim 4. According to the claims on
appeal, a counter as described in, for example, column 4, lines 59-62 of
Chapple is a different element than the benchmark program on the functional
unit(s) on the data processing unit recited in claim 1 and the functional
unit(s) of the data processor executing the benchmark program recited in
claim 4.
12 The Examiner also cites column 4, lines 1-3 of Chapple. Final Act. 7.
That portion of Chapple discloses that "[t]he events that are generated within
the counters unit that can control the execution of control commands are: 1.
a programmable threshold condition was true; 2. a command was triggered
to begin; and 3. a counter overflow or underflow occurred." Chapple, col. 3,
1. 65---col. 4, 1. 3. The Appellant argues that "[t]his portion of Chapple does
not mention the stop command recited in claims 1 and 4." App. Br. 14. We
agree.
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The second portion of Chapple relied on by the Examiner states:
For the counter 306 to actually begin counting and increment,
the start command must first be triggered to begin by detecting
an occurrence of a cache flush (event B shown in FIG. 4(c)).
Immediately following that command the counter block
controller is programmed to stop counting the events and latch
the counted value (shown in FIG. 4(e)) into data register 305.
Chapple, col. 6, 11. 32-38 ( emphasis added).
The Examiner finds that command triggers 102; command, status, &
event registers & control logic 105; registers 106, multiplexers, and other
unidentified logics within the counter blocks correspond to the claimed
functional units. Final Act. 5, 10; Ans. 8. The Examiner, however, does not
find that a "counter block controller" is a functional unit within the scope of
claims 1 and 4. See App. Br. 15 (arguing that both claims 1 and 4 recite that
the data processing operations occur in the functional units).
The third portion of Chapple relied on the Examiner states:
FIG. 5 is a flowchart illustrating an example method of
programming the hardware based event control example
embodiment of the invention shown in FIGS. 3 and 4(a}--4(e).
First, the event to be counted is selected (501). A Start opcode
is sent to the command register with event B as the command
trigger (502). The Command Trigger Indicator (CTI) is
continually checked until event B is detected and the Start
opcode is therefore executing (503 and 504). The Stop opcode
is then sent with event C as the Command trigger (505). The
Command Trigger Indicator is continually checked until event
C is detected and the Stop opcode is therefore executing (506
and 507). Then, the Sample opcode is sent with no command
trigger (508).
Chapple, col. 6, 1. 66-col. 7, 1. 10 ( emphasis added).
The Appellant argues:
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This portion of Chapple does not teach a stop command.
Instead this portion of Chapple teaches a stop opcode followed
by an event (C) as a trigger. Thus counting does not end on the
stop opcode but upon the next C event following the stop
opcode "sent with event C as the command trigger."
App. Br. 16 ( emphasis added).
Claims 1 and 4 recite stopping data processing operations upon
detection of a stop command. App. Br. 19, 20; see also Spec. 22, 11. 8-10
( disclosing that if a stop command is received, the data processor and
counting by the benchmark counter stop). In contrast, Chapple does not
disclose stopping data processing operations upon detection of a stop
opcode. Rather, when a stop opcode is sent, data processing continues.
Thus, the Appellant's argument is supported by the record.
Based on the foregoing, a preponderance of the evidence does not
support the Examiner's finding of anticipation. Therefore, the rejection of
claims 1--4, 6, and 7 under 35 U.S.C. § 102(b) is not sustained.
C. DECISION
The Examiner's decision to reject claims 1--4, 6, and 7 under 35
U.S.C. § 112, first paragraph, as failing to comply with the written
description requirement is affirmed.
The Examiner's decision to reject claims 1--4, 6, and 7 under 35
U.S.C. § 102(b) as anticipated by Chapple is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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