Ex Parte Rozas et alDownload PDFPatent Trial and Appeal BoardOct 10, 201813892931 (P.T.A.B. Oct. 10, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/892,931 05/13/2013 102469 7590 10/12/2018 PARKER JUSTISS, P.C./Nvidia 14241 DALLAS PARKWAY SUITE 620 DALLAS, TX 75254 FIRST NAMED INVENTOR Guillermo J. Rozas UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. SC-12-0709-US 1 4305 EXAMINER HUR,JUNGH ART UNIT PAPER NUMBER 2824 NOTIFICATION DATE DELIVERY MODE 10/12/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@pj-iplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte GUILLERMO J. ROZAS, 1 Jason Golbus, and Chi Keung Lee Appeal2017-011523 Application 13/892,931 Technology Center 2800 Before JEFFREY T. SMITH, MARK NAGUMO, and DEBRA L. DENNETT, Administrative Patent Judges. NAGUMO, Administrative Patent Judge. DECISION ON APPEAL NVIDIA Corporation ("Rozas") timely appeals under 35 U.S.C. § 134(a) from the Final Rejection2 of claims 1-20. We have jurisdiction. 35 U.S.C. § 6. We affirm. 1 The applicant under 3 7 C.F .R. § 1.46, and hence the appellant under 35 U.S.C. § 134, is the real party in interest, identified as Nvidia Corporation. (Appeal Brief, filed 8 April 2017 ("Br."), 3.) 2 Office Action mailed 8 November 2016 ("Final Rejection"; cited as "FR"). Appeal2017-011523 Application 13/892,931 A. Introduction 3 OPINION The subject matter on appeal relates to asynchronous first-in, first-out (FIFO) memory. (Spec. 1 [0001].) Such memories are said to be used to buffer data between devices operating at different clock speeds or in flow control applications where data is stored temporarily for further processing. (Id. at [0002].) According to the '931 Specification, "[i]n asynchronous FIFO memory, read and write cycles use different clocks." (Id. at 2 [0003].) As a result, metastabilities, which arise when a logic device is at neither logic high or logic low, are said to lead to data errors. (Id.) To resolve this problem, designers are said to synchronize the read and write clocks, or to synchronize read and write pointers to the read and write clocks. (Id.) These procedures are said to be complicated by the voltage in the read domain being in general different from the voltage in the write domain. (Id. at 4 [0012].) The inventors seek patent protection for a dynamic multiplexer ( claims 14-7), a method of transitioning between two asynchronous voltage- frequency domains (claims 8-14), and a dual-domain memory spanning a write domain and a read domain ( claims 15-20). The problems of the prior art are said to be addressed by using the dual domain dynamic multiplexer 3 Application 13/892,931, Dual-domain dynamic multiplexer and method of transitioning between asynchronous voltage and frequency domains, filed 13 May 2013. We refer to the "'931 Specification," which we cite as "Spec." 4 The claims in bold font are the independent claims of each set. 2 Appeal2017-011523 Application 13/892,931 "as the transition device for both the voltage transition and the frequency transition." (Id. at [0014], sentence bridging 4--5.) An embodiment of an asynchronous FIFO memory 1005 according to the invention is illustrated in Figure 1, reproduced below. WRITE REGISTER 11Q FIFO MEMORY ARRAY 12.Q WRITE CtOCI<. DISTRIBUTION 150 ·t90 ) 180 r-J READ REGISTER HQ {Figure 1 shows asynchronous FIFO memory 100} FIFO memory 100 comprises write register 110 and FIFO memory array 120, both powered by write voltage supply VDDwrite 170 and write clock distribution CLKwrite 150. FIFO memory array 120 remains entirely in the write domain, powered by the write voltage, and data 190 flows into dynamic multiplexer MUX 130 "as data input into the write domain." (Id. at 6 [0014].) Dynamic multiplexer 130 itself, however, is powered by the read voltage, V ddread, 180, and is clocked by the read clock, 5 Throughout this Opinion, for clarity, labels to elements are presented in bold font, regardless of their presentation in the original document. 3 Appeal2017-011523 Application 13/892,931 CLKread, 160. As indicated in the following discussion, the select lines, which select the data to be input into the multiplexer, are also in the read domain. Figure 2, reproduced below, illustrates an embodiment of dynamic multiplexer ("MUX") 200. {Figure 2 shows a circuit diagram of 3 x 1 dynamic multiplexer 200; thick horizontal line indicating the "dynamic node" of mux 200 added} Data input to MUX 200 is via NMOS pull-down stacks 202-1, 202-2, and 202-3, indicating that it is a 3 x 1 MUX. (Id. at 8 [0019].) Data input signals arrive at data input gates 216-i from FIFO memory array 120 at any time, whereas data select signals arrive at data select gates 218-i "monotonically," i.e., one per cycle. (Id. at [0020].) Pre-charge pull-up 206 is powered by read voltage source Vddread 214. In the words of the '319 Specification, "[o]n the falling edge of pre-charge signal 212, the dynamic node of mux 200 is charged up to the level of read voltage source 214" (id. at 9 [0021]) by pre-charge pull-up 206. Then, when data is present at gate 216-1 of pull-down stack 201-1, and that 4 Appeal2017-011523 Application 13/892,931 pull-down stack is selected by data select gate 218-1 being driven high (id. at 9--10 [0023]), the data is latched into glitch latch 204, with the aid of keeper circuit 208:210, which operates to strengthen logic level high signals and to provide noise immunity (id. at [0022]). Claim 1 is representative and reads: A dynamic multiplexer [200], comprising: a first domain having a first voltage [VDDwrite, 170] and a first clock [CLKwrite, 150], and a second domain having a second voltage [V ddread, 180] and a second clock [CLKread, 160], wherein said first voltage [VDDwrite, 170] is different than said second voltage [V ddread, 180]; a plurality of data [ d, 216-i] and data select input [ ds, 218-i] pairs wherein a data input [d, 216-i] of an input pair of said plurality of data and data select input pairs is in said first domain [VDDwrite, CLKwrite,] and a data select input [ ds, 218-i] of said input pair is in said second domain [V ddread, CLKread,]; and a pre-charge stage [206] in said second domain [V ddread, CLKread,] that is energized upon an edge of said second clock [CLKread, 160], whereby one data and data input pair [216-i, 218-i] is enabled and data latched in said second domain [VDDread, CLKread] upon another edge of said second clock [CLKread, 160]. (Claims App., Br. 12; some indentation, paragraphing, emphasis, and bracketed labels to elements shown in Figures 1 and 2 added.) 5 Appeal2017-011523 Application 13/892,931 The Examiner maintains the following grounds of rejection: 6, 7 A. Claims 1--4 and 6-14 stand rejected under 35 U.S.C. § 103 in view of the combined teachings of Lin 8 and Mellinger. 9 Al. Claim 5 stands rejected under 35 U.S.C. § 103 in view of the combined teachings of Lin, Mellinger, and Klapproth. 10 B. Claims 15-20 stand rejected under 35 U.S.C. § 112(b). 11 B. Discussion The Board's findings of fact throughout this Opinion are supported by a preponderance of the evidence of record. Initially, as the Examiner finds (Ans. 3, § 2), Rozas does not dispute Rejection B of claims 15-20. We therefore summarily affirm Rejection B. The Examiner finds that Lin describes, in Figure 2, shown on the following page, a dynamic multiplexer having first and second domains with distinct voltages V dd2 ( corresponding to VDDwrite, 170) and V dd1 6 Examiner's Answer mailed 14 July 2017 ("Ans."). 7 Because this application was filed after the 16 March 2013, effective date of the America Invents Act, we refer to the AIA version of the statute. 8 Jentsung Lin et al., Dual-voltage domain memory buffers, and related systems and methods, U.S. Patent Application Publication 2013/0182515 Al (18 July 2013), based on an application filed 19 December 2012. 9 Todd W. Mellinger et al., Dynamic logic MUX, U.S. Patent No. 6,549,060 Bl (2003). 10 Peter Klapproth et al., Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions, U.S. Patent No. 5,590,354 (1996). 11 The Examiner has indicated that the claimed subject matter recited in claims 15-20 is allowable over the prior art of record. (FR 11-12.) 6 Appeal2017-011523 Application 13/892,931 ( corresponding to VD Dread, 180) and distinct clocks (write clock signal 22 and read clock signal 36). (Ans. 5, 11. 5-8.) The Examiner finds Lin describes data----one of data signals 32(N}-in first domain V dd2, paired with a data select input signal (i.e., a corresponding select signal within multiplexing circuit READ_MUX 30), which is in second domain V dd1. {Lin Figure 2 is shown below} i . . . . ;:;,\(,: ,,;,,,;,:.;; ,.,-:,:~ . f.,.,---:iB ' lli ' ' ' ' ' ' ' ' ' ' ' ' 4~\·1 )~\ I : \(1_,;:· , ...... ,. ............................ ~ .. l ' ' ' ~':;::;F~*~::;;;;i.,·~~.:l~vcn~ ........ {: .. i .. ~ ... .;. \•( '·'·-,.:.~·:' ('(:,:·:~ -~:·: ·.f':.:::f:'~~ ts,,,.__ ' : : L':i ii ~YIB ~R_N_JC_~~~~- l : :2~e-J '----....,=..----' I : ...,,.-.-~J.-~ t '------------ -- ------------------------------- __________________ t {Figure 2 shows a block diagram of a dual voltage domain asynchronous memory buff er 10' ( annotations added)} The Examiner finds that Lin is silent about the details of read device 26, and therefore does not describe the pre-charge stage in the second domain and the clocking of the enabling of a data and data select input, and of the data latching recited in the final portion of claim 1. (J d. at para. bridging 5-6.) The Examiner finds these deficiencies are disclosed by Mellinger, in the dynamic multiplexer (MUX) shown in Figure 2 ( on the next page). 7 Appeal2017-011523 Application 13/892,931 {Mellinger Figure 2 is shown below} .--230 _ .... __ f·231 ----f'~~~,~~~--,,.~~~-------i I : INAC->---,: !NBC:::::--,: l i l : I i .,. .1': : ~ i: I I ; : I : I : 2Q~I j; I 20~~11 -·218 ': .:I';:· i ~~ .. i r.-.·:~-~ i L212 i----<1---: CK 1,<210: ! !>201: ! .,}--203 jp---t ... f:-,----+ c:::> ···1-.. ----.l.- -l:~·: ••• ' SELBc::::-;----l- ,r_· : l ~ 1 '-'220! OUT ' - ~-------------:_1~ --------------- ~ --"14 : --------C::,> ...... ¥.LJ!5J_~ · .......... ________ ...... J ....... • • • _Ml,J:l<_IN ..... -....... ..9 . : • . l 224, r ·,,,,,,11.,... __ pg_, ~{i>,,---H: i 216 -222 l ·· ......... ········· ··········---- ·············------ ···-----------1.>-22a ____ t-i_c.::_ts____________________ ------------: ( " +, {Figure 2 shows a circuit diagram of a dynamic multiplexer having a latched dynamic node PD ( annotations added)} The Examiner finds Mellinger describes a multiplexing circuit (230, 231), with data (INA) and data select input (SELA) pairs, with a read circuit comprising a pre-charge stage 210 that is energized on the falling edge of clock CK, and selected data ( e.g., from 230) latched with cross-coupled inverters 218 and 220 on the rising edge of CK. (FR 6, 11. 3-7.) The Examiner reasons that it would have been obvious "to use the multiplexing circuit and the read circuit of Mellinger for the multiplexing circuit and the read circuit in fig. 2A of Lin" in order to obtain the reliable, low-leakage characteristics provided by Mellinger. (Id. at 11. 11-16, capitalization omitted.) Rozas urges the Examiner erred harmfully in at least two ways regarding the teachings of Lin. First, in Rozas's view, the Examiner erred in equating data signals 32(N) and read address signals 28 disclosed by Lin with the data input pairs recited in claim 1. (Br. 6, last para.) The data input pairs recited in claim 1, Rozas insists, are "actual inputs, i.e., NMOS pull- down stacks 201-1," etc. (Id.) 8 Appeal2017-011523 Application 13/892,931 This argument is not persuasive of harmful error for at least three reasons. First, each example presented in the '931 Specification is presented as a diagram (Spec. Figure 1, 6-7 [0016]) or a schematic (id. Figure 2, 8 [0019]; Figure 3, 10 [0024]) ofan "embodiment" ofa circuit or device. The Specification states specifically that "[ t ]hose skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments." (Id. at 13 [0030].) Thus, the embodiments merely serve to illustrate the invention: they do not serve to define the invention in any exclusive way. Our reviewing court has repeatedly "cautioned against reading limitations into a claim from the preferred embodiment described in the specification, even if it is the only embodiment described, absent clear disclaimer in the specification." In re Am. Acad. Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004) (citations omitted). Second, and perhaps more fundamentally, the claims are written almost entirely in functional language. Rozas has not directed our attention to any express definitions of these terms in the Specification or in the record. Thus, the Examiner applied correctly a broad interpretation of the claim language consistent with the disclosure. As our reviewing court explained nearly five decades ago, "'[f]unctional' terminology may render a claim quite broad. By its own literal terms a claim employing such language covers any and all embodiments which perform the recited function." In re Swinehart, 439 F.2d 210,213 (CCPA 1971). Third, the difference between signals and the "actual inputs"-by which Rozas apparently means the element or device that sends or receives the signal is, absent more precise limitations, of little moment, as there is no 9 Appeal2017-011523 Application 13/892,931 question that some structure must perform these functions in any embodiment of the devices described by Lin and by Mellinger. The second defect of Lin, according to Rozas, is that Lin does not teach that any of the signals (32(N)) input to the MUX corresponds to any of Lin's select signals (read address signals 28). (Br. 7.) Rozas presents a model of the functioning of the multiplexer and concludes that there is not a correspondence that is equivalent to a data input and a data select input as a pair, as required by claim 1. (Id.) This argument is not persuasive of harmful error for at least two reasons. First, Rozas does not explain why, in the context of a FIFO memory buffer, the general description provided by Lin in paragraph [0007] does not pair a read address for a specific latch output 32(0}-32(N-1) with data from a corresponding latch bank 12(0}-12(N-1). For example, if a given bit is stored in latch bank 12(6), the read pointer will be set to read corresponding data 32(6). Second, the model proffered by Rozas is not supported by reference to any evidentiary authority of record. As such, we decline to accord the argument significant weight. In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974) ("Attorney's argument in a brief cannot take the place of evidence."). Notably, with respect to claim 1, Rozas does not challenge any of the Examiner's findings regarding Mellinger, other than Mellinger's failure to cure the perceived defects of Lin. (Br., para. bridging 7-8.) Similarly, with regard to the remaining claims dependent on claim 1, including separately rejected claim 5, Rozas does not challenge the Examiner's additional findings, but focuses on the alleged errors regarding Lin. 10 Appeal2017-011523 Application 13/892,931 As explained supra, we have not been persuaded of harmful error in the Examiner's analysis of Lin. We therefore affirm the rejection of claim 1 and its dependent claims. Regarding independent claim 8, which is drawn to a method of transitioning between two asynchronous voltage-frequency domains, Rozas argues that "there is no teaching or suggestion in Mellinger, that its MUXIN signal is a readline." (Br. 9, 1. 19.) Similarly, Rozas urges that Lin does not teach or suggest a readline. (Id. at 1. 20.) Rozas "submits" that one skilled in the art would understand that Lin's flip-flop latch banks would not include a readline, where a readline is used as depicted in Figure 3 of the '931 Specification. (Id. at 11. 20-25.) The difficulties with these arguments are similar to those already discussed. Rozas cites no evidence in support of these arguments. Moreover, Rozas does not direct our attention to a definition of the term "readline" in the Specification or elsewhere in the record. In particular, Rozas does not explain why the process recited in claim 8 does not read on the functioning of the MUX in Figure 2, supra. Indeed, the description of the MUX provided by Mellinger, particularly the operation of the precharge phase and the evaluate phrase (Mellinger col. 3, 11. 6-50), appears to be similar to the dynamic MUX described by Rozas. We conclude that Rozas has not shown harmful error in the rejection of claim 8, which we therefore affirm. 11 Appeal2017-011523 Application 13/892,931 C. Order It is ORDERED that the rejections of claims 1-20 are affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED 12 Copy with citationCopy as parenthetical citation