Ex Parte Roy

Patent Trial and Appeal Board

Jan 24, 2018

14041449 (P.T.A.B. Jan. 24, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/041,449 09/30/2013 ANIRBAN ROY AM20802TP 9731
23125 7590 01/26/2018
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/OE62
AUSTIN, TX 78735
EXAMINER
PATEL, REEMA
ART UNIT PAPER NUMBER
2812
NOTIFICATION DATE DELIVERY MODE
01/26/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANIRBAN ROY
Appeal 2017-002579
Application 14/041,449
Technology Center 2800
Before KAREN M. HASTINGS, JAMES C. HOUSEL, and
MICHAEL G. McMANUS, Administrative Patent Judges.
HASTINGS, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35U.S.C. § 134 from the Examiner’s
rejection of claims 1, 3—16, and 18—20. We have jurisdiction over the appeal
pursuant to 35 U.S.C. § 6(b).
WE AFFIRM.
1 The real party in interest is stated to be NXP Semiconductors (Appeal Br.
3).
Appeal 2017-002579
Application 14/041,449
Claim 1 is illustrative of the claimed subject matter:
1. A method of making a semiconductor structure,
comprising:
forming first and second active regions in a
substrate;
patterning a first polysilicon layer on the substrate to
form a first floating gate over the first active region
in the substrate and a second floating gate over the
second active region in the substrate;
filling an opening between the first and second floating
gates with a dielectric material;
etching back the dielectric material so that a height of a
remaining portion of the dielectric material is less
than a height of the first and second floating gates;
depositing an interlayer dielectric layer over the first and
second floating gates and the remaining portion of
the dielectric material;
depositing a second polysilicon layer over the first and
second floating gates, the interlayer dielectric, and
the remaining portion of the dielectric material to
form a word line for the first and second floating
gates; and
etching the first and second polysilicon layers and the
interlayer dielectric layer using a single mask to
form the first and second floating gates and the
control gate.
Appeal Br. 15 (Claims Appendix).
Independent claims 8 and 15 are directed to similar methods of making
a semiconductor structure (Claims Appendix).
The Examiner maintains the following rejections under
35U.S.C. § 103:
1) Claims 1, 3—6, 8—10, 12 and 14 as unpatentable based on Wu (US
6,621,119 Bl, issued Sept. 16, 2003 “Wu”), Roberts et al. (US
2
Appeal 2017-002579
Application 14/041,449
5,376,577; issued Dec. 27, 1994 "Roberts") and Ozawa et al. (US
5,869,858; issued Feb. 9, 1999 "Ozawa");
2) Claims 7 and 11 as unpatenable over Wu, Roberts, Ozawa, and
Wang (US 7,719,050 Bl, issued May 18, 2010 “Wang”);
3) Claims 8, 12—13, 15—16 and 18—19 as unpatentable over Byun et al.
(US 7,952,134 B2; "Byun"), Wu, and Ozawa;
4) Claim 20 as unpatentable over Byun, Wu, Ozawa, and Wang.
ANALYSIS
Upon consideration of the evidence on this appeal record and each of
Appellant’s contentions, we find that the preponderance of evidence on
this record supports the Examiner’s conclusion that the subject matter of
Appellant’s claims is unpatentable over the applied prior art. We sustain the
Examiner’s § 103 rejections essentially for the reasons set out by the
Examiner in the Answer.
We add the following for emphasis.
Rejections 1 and 2 based on Wu, Roberts, and Ozawa
Appellant’s main argument is that Wu and Roberts “are not even
analogous art” (Appeal Br. 10) and there is no reason to use the teaching of
Roberts relating to the order of forming an active region and depositing a
polysilicon layer to Wu (App. Br. 11; Reply Br. 3). These arguments do
not appear to fully address the applied prior art as a whole, and are not
persuasive for reasons set out by the Examiner (Ans. 3, 4 (explaining that
both references are directed to manufacturing semiconductor devices, and
reliance on Roberts to exemplify an alternative order of steps for Wu is
permissible)).
3
Appeal 2017-002579
Application 14/041,449
Furthermore, as pointed out by the Examiner, there are only three
choices for the disputed order of the steps of forming the active regions and
patterning a first polysilicon layer over these regions (Ans. 3 (form active
regions first, form active regions after patterning polysilicon layer, or
perform the two steps simultaneously)). Notably, it has been held that a
specific order of steps in manufacturing a device may be prima facie obvious
when “[tjhere is nothing in the instant record which indicates that the
particular order of steps produces results differing in any way from those
which would be brought about if another order of steps were followed.” In re
Hampel, 162 F.2d 483, 485 (CCPA 1947); see also, In re Burhans, 154 F.2d
690, 692 (CCPA 1946) (selection of any order of performing process steps is
prima facie obvious in the absence of new or unexpected results); In re
Gibson, 39 F.2d 975, 976 (CCPA 1930) (Selection of any order of mixing
ingredients is prima facie obvious.); Ex parte Rubin, 128 USPQ 440, 441
(Bd. Pat. App. & Int. 1959) (Prior art reference disclosing a process of
making a laminated sheet wherein a base sheet is first coated with a metallic
film and thereafter impregnated with a thermosetting material was held to
render prima facie obvious claims directed to a process of making a
laminated sheet by reversing the order of the prior art process steps.).
Appellant has not directed us to any evidence or persuasive technical
reasoning that the required order of steps produces results differing in any
way from those which would be brought about if another order of steps were
followed.
Appellant does not present additional arguments for any of the other
claims, including those rejected in rejection 2. Accordingly, we affirm the
Examiner’s § 103 rejections listed as 1 and 2 above.
4
Appeal 2017-002579
Application 14/041,449
Rejections 3 and 4 based on Byun, Wu, and Ozawa
Appellant’s argument focuses on a lack of motivation to use a single
mask step as exemplified in Ozawa in Byun’s manufacturing method,
because the structure of Byun is different from that of Ozawa (Appeal Br.
12) , and the method used in Byun “would have to be changed significantly to
allow the incorporation of the single mask etching of Ozawa” (Appeal Br.
13) .
Appellant has not persuasively shown that the Examiner’s reliance
upon Ozawa to exemplify the obviousness of etching the first and second
polysilicon and the interlayer dielectric layer of the Byun/Wu device using a
single mask as recited in claim 8 in order to reduce the overall number of
masking steps (e.g., Ans. 4, 5; Final Action 8-10) is unreasonable. “It is well
settled that a prior art reference is relevant for all that it teaches to those of
ordinary skill in the art.” In re Fritch, 972 F.2d 1260, 1264 (Fed. Cir. 1992).
Appellant has also not adequately responded to the Examiner’s position that
since “the structures of Byun and Ozawa are similar in that they both involve
a step of patterning a floating gate, an interlayer dielectric, and a control gate,
one of ordinary skill in the art would have been motivated to modify the
invention of Byun with the single mask etching step of Ozawa.” (Ans. 5;
Reply Br. generally).
Appellant has not shown error in the Examiner’s determination that
one of ordinary skill in the art, using no more than ordinary creativity, would
have used a single mask etching step for two semiconductor layers and a
5
Appeal 2017-002579
Application 14/041,449
dielectric interlayer as exemplified in Owaza in manufacturing the device of
the Byun/Wu combination. In re Kubin, 561 F.3d 1351, 1360 (Fed. Cir.
2009) (obviousness only requires a reasonable expectation of success). See
also In re Keller, 642 F.2d 413, 425 (CCPA 1981) (“The test for obviousness
is not whether the features of a secondary reference may be bodily
incorporated into the structure of the primary reference .... Rather, the test
is what the combined teachings of the references would have suggested to
those of ordinary skill in the art.”); In re Nievelt, 482 F.2d 965, 968 (CCPA
1973) (“Combining the teachings of references does not involve an ability to
combine their specific structures.”).
Accordingly, we affirm the Examiner’s rejections.
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
6