Ex Parte Rhee et al

Patent Trial and Appeal Board

Aug 13, 2013

11622166 (P.T.A.B. Aug. 13, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/622,166 01/11/2007 WOOGEUN RHEE YOR920060522US1
(163-154)
2474
49267 7590 08/14/2013
TUTUNJIAN & BITETTO, P.C.
425 Broadhollow Road, Suite 302
Melville, NY 11747
EXAMINER
HILTUNEN, THOMAS J
ART UNIT PAPER NUMBER
2816
MAIL DATE DELIVERY MODE
08/14/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte WOOGEUN RHEE and DANIEL J. FRIEDMAN
____________

Appeal 2011-000482
Application 11/622,166
Technology Center 2800
____________

Before CAROLYN D. THOMAS, DENISE M. POTHIER, and GREGG I.
ANDERSON, Administrative Patent Judges.

ANDERSON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1 and 11. Claim 3 is cancelled. Claims 4, 13, and 14 are
objected to as dependent on currently rejected claims. Claims 2, 5-10, 12,
and 14-34 have been withdrawn in response to a restriction requirement. We
have jurisdiction under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellants’ invention relates measuring system parameters used in the
fabrication and testing of integrated circuit chips. More specifically, the
invention uses phase-locked loop (PLL) circuits to output phase error
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signals. The signals are stored and PLL jitter is estimated based on patterns
in the phase error signals. See generally Spec. ¶¶ [0030]-[0034]. Claim 1 is
illustrative:
1. An apparatus, comprising

a phase-locked loop (PLL) circuit including a phase-frequency
detector configured to output phase error signals;

a phase error monitor circuit configured to determine instantaneous
peak phase error by logically combining the phase error signals and
comparing pulse widths of the logically combined phase error signals to a
programmable delay time at each reference clock cycle to determine
instantaneous phase error change, the phase error monitor circuit
comprising:

a storage element configured to store the instantaneous phase
error change; and

a pattern analyzer coupled to the storage element to determine
patterns in the instantaneous phase error changes to estimate PLL jitter.

THE REJECTIONS
1. The Examiner rejected claim 11 under 35 U.S.C. § 103(a) as being
unpatentable over Wang (US 2008/0013664 A1, published Jan. 17, 2008,
filed Jul. 11, 2006) and Hui (US 6,914,492 B2, issued Jul. 5, 2005). Ans. 4-
5.2
2. The Examiner rejected claim 11 under 35 U.S.C. § 103(a) as being
unpatentable over Crook (US 6,549,079 B1, issued Apr. 15, 2003) and Chiu
(US 6,483,361 B1, issued Nov. 19, 2002). Ans. 6-7.

1 The Examiner mistakenly included canceled claim 3.
2 Throughout this opinion, we refer to (1) the Appeal Brief filed March 1,
2010 (“Br.”); and (2) the Examiner’s Answer mailed June 25, 2010 (“Ans.”).
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ISSUES
(1) Under § 103, has the Examiner erred in rejecting claim 1 by
finding that Wang and Hui collectively would have taught or suggested “a
pattern analyzer coupled to the storage element to determine patterns in the
instantaneous phase error changes to estimate PLL jitter”?
(2) Under § 103, has the Examiner erred in rejecting claim 11 by
finding that Crook and Chiu collectively would have taught or suggested “a
phase error monitor circuit configured to determine instantaneous peak
phase error amplitude”?

ANALYSIS
Rejection of Claim 1 Under 35 U.S.C. § 103
On this record, we find no error in the Examiner’s obviousness
rejection of claim 1 which recites, in pertinent part, “a pattern analyzer
coupled to the storage element to determine patterns in the instantaneous
phase error changes to estimate PLL jitter.” The Examiner relies on Wang’s
teaching of a controller 328 and counter 326. Ans. 5, 9-11 (citing Wang, ¶
[0017], Fig. 3). As broadly stated in claim 1, the Examiner finds controller
328 and counter 326 function as a pattern analyzer coupled to the storage
elements identified in Figure 3 at 324, delay (D) flip flops(FF). Ans. 10.
The phase error output of the controller, ERRPD of Figure 3, is based on
reading data from the flip flops 324, CDFF. Id. (citing Wang, ¶¶ [0018]-
[0020]). The Examiner maps reading data to analyzing a pattern, as recited
in claim 1. Id.
The Examiner also finds each Dflip flop 324 stores “instantaneous
phase error change” information as recited in the disputed limitation of claim
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1. Ans. 10-11. The Examiner finds an instantaneous phase change error is
detected by Wang’s teaching that an output signal S2 from XOR gate 316 of
Figure 3 is pulsed high anytime there is a phase error present. Id. (citing
Wang, ¶ [0016], ll. 6-8 and 10-11). The D flip flops 324 latch, i.e., “store,”
the value of S2. Id. The Examiner concludes that the controller determines
patterns in the instantaneous phase error change by taking the output of the
information stored in the D flip flops 324, CDFF, to estimate the total phase
error, ERRPD. Id. (citing Wang, ¶ [0016], ll. 12-13 and ¶ [0017], ll. 17-21).
As to the recitation of estimating phase-locked loop (PLL) jitter, the
Examiner finds that one of ordinary skill in the art would understand that the
total phase error of a PLL system is caused by PLL jitter. Ans. 11. Thus, by
estimating the total phase error of a PLL system one would also estimate, at
least in part, PLL jitter. Id.
Appellants allege that determining the phase error, as Wang teaches,
is not the same as “determining patterns in phase error or as estimating
jitter.” Br. 12. Appellants further contend a phase error calculation is not
representative of a pattern because “there is no reference to any data outside
that particular point.” Id. The Appellants’ Brief states jitter is a “short-term
variation[s] of a signal with respect to its ideal position in time.” Id. at 13.
Thus, Appellants argue Wang does not address jitter because jitter dictates
that phase error be tracked over a period of time. Br. 13 (citing Wang ¶
[0018]).
We begin with Appellants’ contention that Wang’s detection of phase
error is not detecting a pattern of phase error. At the outset, we note that the
disputed recitation, “to determine patterns . . .,” merely describes the
intended use of the recited pattern analyzer and the pattern analyzer need
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only have the ability to perform this function. See In re Schreiber, 128 F.3d
1473, 1478 (Fed. Cir.1997). As illustrated below, Wang has such a
capability.
The premise of the argument is that only discrete data, “a particular
point” as opposed to a pattern, is measured in Wang’s phase error
measurement circuit. We agree with the Examiner that the claims do not
require the tracking of instantaneous phase error changes. Ans. 10. The
language recited in claim 1 does not limit the scope of the claim as argued
by Appellants (e.g., Appellants contends that claim 1 tracks the phase error
over a period of time or tracking of instantaneous phase error changes). See
Br. 12-13.
Also, Appellants’ argument does not point to anything in Wang that
would limit its teaching to a particular point. Indeed, Wang is capable of
analyzing multiple signals using a multi-phase clock generator 322 (see
Wang, ¶¶ [0017], [0020]). Wang further provides for count clocks for
different phases. Wang, ¶ [0017]. This teaching of Wang is very similar to
the use of five reference clock periods described in the Specification. Spec. ¶
[0040], ll. 10-13. The five clock periods are described as part of providing
“patterns” for the “pattern analyzer.” Id., l. 13. We also note the circuit
shown in Appellants’ drawings at Figure 4 is very similar to the circuit
taught by Wang Figure 3 and both output a phase error. See In re Best, 562
F.2d 1252, 1255 (CCPA 1977).
We also agree with the Examiner that the person of ordinary skill in
the art would understand there is an association between jitter and phase
error discussed in Wang. Ans. 11. Thus, given the creative steps and
inferences of an ordinary artisan would employed, we find that Wang has the
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ability to estimate PLL jitter. Jitter in digital communications is “distortion
caused by lack of synchronization of signals.” Microsoft Computer
Dictionary, pg. 373 (2002).
Appellants do not persuade us of any Examiner error and we sustain
the Examiner’s rejection of claim 1.

Rejection of Claim 11 Under 35 U.S.C. § 103
On this record, we find no error in the Examiner’s obviousness
rejection of claim 11 which recites, in pertinent part, “a phase error monitor
circuit configured to determine instantaneous peak phase error amplitude.”
The Examiner finds the disputed limitation present in Chiu. Ans. 7,
12-14. Chiu’s Figure 3, a lock detector circuit 700, maps to the disputed
limitation. Ans. 7. The Examiner cites to the parts of the lock detector
circuit of Chiu, a first stage filter 701, a second stage filter 702, a AND
circuit 703, and a detector circuit 704 as determining the peak phase error
amplitude. Ans. 6-7 (citing Chiu, col. 6, ll. 7-27). The time delay circuit
702 sets a tolerance level or threshold for the desired phase error. Id. Chiu
teaches that the lock detector circuit 700 receives an input comparing the
pulses from the signals generated by the first and second circuits to the
threshold. Id. Phase error amplitude is indicated by whether phase detector
signals, down and up pulses, overlap with the threshold set by delay circuit
702. Id.
The Examiner also finds a generic lock detector operates to teach the
disputed limitation. Ans. 13 (citing Chiu, col. 1, ll. 54-67 and col. 2 ll. 1-
24). “If a phase difference (i.e., phase error) between a reference signal and
feedback signal is greater than the magnitude of a desired phase error (i.e.,
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the lock detector threshold) the detector indicates an out-of-lock, [i.e., phase
(and frequency)], situation and if the phase difference is less than a phase
error the lock detector indicates an in-lock situation.” Id. (citing Chiu, col.
1, ll. 61-65 and col. 2, ll. 6-24). The Examiner concludes that, as would be
understood by one of ordinary skill in the art, the “amplitude” of a signal
indicates the quantity of a measured variable (i.e., the magnitude of a
signal). Ans. 13.
Appellants argue all that Chiu teaches “is a simple, binary response
that shows whether or not there is a lock.” Br. 16. Appellants go on to state
that a lock detector has no “inherent reason” to determine phase error
amplitude because it is unnecessary for determination of a lock condition.
Id. Lock detectors, according to Appellants, do not deal with phase error
amplitude. Id.
At its core, Appellants’ argument is that Chiu teaches a lock detector
circuit which does not “determine a phase error amplitude” as claimed.
Appellants’ argument is flawed because Chiu teaches a lock detector circuit
700 with a detection circuit 704. Chiu, col. 4, ll. 64-col. 5, l. 2, Fig. 3. The
Examiner specifically finds the lock detector circuit of Chiu and the phase
detector circuit 704 determines the peak phase error amplitude. Ans. 6-7
(citing Chiu, col. 6, ll. 7-27).
The Examiner further finds that Chiu compares signals to determine if
the signals are out-of-lock or in lock, which gauges any phase error. Ans. 6-
7, 13 (citing Chiu, col. 6, ll. 7-27; col. 1, ll. 61-65; col. 2, ll. 6-24). In-lock
means the signal pulses are within the threshold phase error. Chiu, col. 6, ll.
7-27. Out-of-lock means the signal pulse is outside of the threshold. Id.
We also note that a “lock” between the feedback signal and the reference
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signal (e.g., a threshold for the phase error) means the two signals must be in
phase (frequency). Chiu, col. 1, 38-40. We further note that Appellants
describe and show the claimed invention, an Instant Phase Error Detector
(IPED), form part of a lock detector. Spec. ¶¶ [0024], [0045]; Fig. 10.
The Examiner finds that a person of ordinary skill would have
recognized that the amplitude of the phase error is a measured variable.
Ans. 13. The magnitude of the phase error determined in the circuit taught
by Chiu would also be a measured variable. Id. Appellants do not respond
to this finding, which we find rationally based.
Appellants’ arguments do not persuade us of Examiner error in
rejecting claim 11 and we therefore sustain the rejection.

CONCLUSION
The Examiner did not err in rejecting claims 1 and 11 under § 103.

ORDER
The Examiner’s decision rejecting claims 1 and 11 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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