Ex Parte Purkayastha et al

Patent Trial and Appeal BoardNov 1, 2018

14192683 (P.T.A.B. Nov. 1, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/192,683 02/27/2014 144016 7590 11/05/2018 Sheridan Ross P.C. 1560 Broadway, Suite 1200 Denver, CO 80202 FIRST NAMED INVENTOR Saugata Das Purkayastha UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 5887-470 5877 EXAMINER BIRKHIMER, CHRISTOPHER D ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 11/05/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): e-docket@sheridanross.com mreno@sheridanross.com mellsworth@sheridanross.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte SAUGATA DAS PURKA Y ASTRA, LUCA BERT, PHILIP K. WONG, and ANANT BADERDINNI Appeal2018-003534 Application 14/192,683 1 Technology Center 2100 Before ERIC B. CHEN, MATTHEW R. CLEMENTS, and SCOTT E. BAIN, Administrative Patent Judges. CLEMENTS, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. Â§ 134(a) from the Examiner's Final Rejection of claims 1-20. We have jurisdiction under 35 U.S.C. Â§ 6(b). We REVERSE. 1 Appellants identify the real party in interest as "Avago Technologies General IP (Singapore) PTE., LTD." App. Br. 1. Appeal2018-003534 Application 14/192, 683 STATEMENT OF THE CASE Appellants' invention relates to "improving the performance of sequential I/0 [(input/output)] operations[,] such as those ... directed by a host computer to a data store supported by both volatile and non-volatile storage elements." Spec. ,r 9. "The method includes ... initializing a paging table in the host to correspond to ... a volatile memory element [(VME)] coupled to [a] host bus adapter [(HBA).]" Id. at ,r 10. The admitted prior art (APA) and all disclosed embodiments include a host, paging table within the host, and VME mapped by the paging table. Figs. 1- 14. The APA and all embodiments also provide a storage controller that pairs the VME with a non-volatile memory element (NVME) and controls their exchange of data. Id. at ,r,r 7-8, 34, 42, 60; Figs. 1, 3, 8, 14. The APA and all embodiments place the storage controller, VME, and NVME within the HBA, which is separate from the host. Id. The improvement to the APA lies partly in the manner of exchanging data between the VME and NVME. Id. at ,r 27 et seq. Claims 1, 14, and 20 are independent. Claim 1 is illustrative and reproduced below. 1. A method for dynamically managing a virtual address space disposed in a host, the virtual address space corresponding to data accessible to a host bus adapter for the host, the method comprising: initializing a paging table which is disposed in the host to correspond to a first portion of available storage capacity of a volatile memory element coupled to the host bus adapter, the first portion of the volatile memory element containing first 2 Appeal2018-003534 Application 14/192, 683 information stored in a non-volatile memory element, wherein the method further includes: when an application executing in the host triggers a fault by requesting access to a page that is not present in the volatile memory element; instructing the host bus adapter to transfer second information from a region of the non-volatile memory element to a second portion of the volatile memory element, the second information defining a most recently transferred region and including the page that is not present in the volatile memory element as defined by the fault; modifying the paging table to include a reference to the most recently transferred region; and updating the virtual address space to reflect the reference in the paging table. App. Br. 20 (Claims Appx.). THE REJECTIONS Claims 1--4, 10, 14, 15, 17, and 20 stand rejected under 35 U.S.C. Â§ I02(a)(l) as anticipated by Hyde (US 2013/0297885 Al; published Nov. 7, 2013). Final Act. 2-12 (May 25, 2017). Claims 5-9, 18, and 19 stand rejected under 35 U.S.C. Â§ 103 as unpatentable over Hyde and Blandy (US 5,390,315; issued Feb. 14, 1995). Final Act. 13-16, 18-21. Claims 11-13 and 16 stand rejected under 35 U.S.C. Â§ 103 as unpatentable over Hyde and Kline (US 5,802,341; issued Sept. 1, 1998). Final Act. 16-18. 3 Appeal2018-003534 Application 14/192, 683 ISSUE Did the Examiner err in interpreting the claimed "host," as recited in independent claims 1, 14, and 20, to encompass the system formed of Hyde's hosts 210,220,225, network 260, and storage controller 240? EXAMINER'S FINDINGS The Examiner reads the claimed "host" on the system of Hyde's hosts 210, 220, 225, network 260, and storage controller 240. See e.g., Final Act. 3 ( claim 1 ); Ans. 3--4. The Examiner also reads the claimed "host bus adapter" and on Hyde's storage controller 240, reads the claimed "volatile memory element coupled to the host bus adapter" on Hyde's cache 245, and reads the claimed "paging table" on Hyde's storage map/DGIM 259. Id. Specifically, the Examiner finds that elements 210, 220, 225 ( each labeled in Hyde as a "Host") "work together" with network 260 and storage controller 240 "to form a host ... to share the resources stored on [storage 230]." Ans. 3; see also id. at 4 ("Together items 210,260, and 240 are considered a host since the combination comprises a general system that is used to manage and access the data on storage devices 230a- 230n."). Although network 260 and storage controller 240 are not described as "hosts" in Hyde, the Examiner finds the claims and Specification do not "prevent[] a storage controller and/or a network [from being] considered part of a host system." Id. at 3, 5-6 ( citing a Wikipedia article that states a supercomputer can comprise thousands of processors sharing data over a network). 4 Appeal2018-003534 Application 14/192, 683 APPELLANTS' CONTENTIONS Appellants argue the Examiner erred in reading the claimed "host" on Hyde's system. See e.g., App. Br. 5-9 (claim 1). Specifically, Appellants contend: [N]o reasonable interpretation of the term 'host' in light of the specification-and in light of Hyde itself-would designate element 240 (which includes the alleged paging table 259) as a host, or would cobble together host 210, element 260, and storage controller 240 and label the resulting conglomeration as a 'host.' Id. at 5---6. Presenting all figures of the present application as support, Appellants further contend: [T]he term "host" is used in its ordinary and customary meaning throughout the specification (see, e.g., Specification at paragraphs [0003]-[0006]; paragraphs [0034]-[0036]; FIGs. 1- 14; etc.), and the written description clearly indicates this meaning, and therefore the term "host" in claim 1 has that ordinary and customary meaning-a meaning which would be understood by anyone practicing in the art. Id. at 6 (underlining omitted). ANALYSIS We agree that the Examiner erred in interpreting the claimed "host" to read on host 210, host 220, host 225, network 260, and storage controller 240. Specifically, the Examiner erred by interpreting the "host" as including the claimed "host bus adapter" and corresponding "volatile memory element." 5 Appeal2018-003534 Application 14/192, 683 As instructed by our reviewing court, "a proper claim construction analysis endeavors to assign a meaning to a disputed claim term 'that corresponds with ... how the inventor describes his invention in the specification."' In re Power Integrations, Inc., 884 F.3d 1370, 1377 (Fed. Cir. 2018) (quoting In re Smith Int'!, Inc., 871 F.3d 1375, 1382-83 (Fed. Cir. 2017) ). The inventors describe and illustrate the AP A and all disclosed embodiments as comprising: a host computer having a paging table and application; and a separate host bus adapter having a storage controller, volatile memory element, and non-volatile memory element. Spec. ,r,r 34, 42, 56; Figs. 1, 3, 8, 14. Moreover, all of Appellants' figures depict the host bus adapter as separate from the host and connected by a "memory bus or a standard input/output (I/0) bus 15 for peripheral devices (e.g., the peripheral component interconnect express (PCie))" (Spec. ,r 3), "an input/output (I/0) bus 115[, 815] or a peripheral bus such as a PCie bus" (id. at ,r 42), or "bus 1420" (id. at ,r 56). Figs. 1-12, 14. Thus, as Appellants argue, the inventors repeatedly and only describe the host as distinct and separate from the host bus adapter and volatile memory element. See supra (Appellants' Contentions); see also supra 2 ( description of the invention); In re Power, 884 F.3d at 1377 ("Notably, moreover, every embodiment ... shows a counter that passes ... "). Technical dictionaries from the relevant time period are consistent with Appellants' argument that a person of ordinary skill in the art at the time of invention would not have understood the "host" of the claims to encompass the "host bus adapter" of the claims. See Phillips v. A WH Corp., 415 F.3d 1303, 1318 (Fed. Cir. 2005) ("We have especially noted the help 6 Appeal2018-003534 Application 14/192, 683 that technical dictionaries may provide to ... better understand ... the way in which one of skill in the art might use the claim terms."). The Microsoft Computer Dictionary defines a host as "a computer" that "provides services, such as news, mail, or data, to computers that connect to it," and a host bus adapter as "a device for connecting a peripheral to the main computer." Microsoft Computer Dictionary, 5th ed., 2002. Collectively, and like Appellants' Specification, the above definitions convey that a "host bus adapter" is different than a "host," and, therefore, are consistent with Appellants' argument that a person of ordinary skill in the art reading Appellants' Specification and claims would not have understood the recited "host" to encompass the recited "host bus adapter." In light of the foregoing considerations, we conclude a person of ordinary skill in the art would understand the present invention's host as distinct and separate from the invention's host bus adapter and volatile memory element. The claim language also recites the element "host bus adapter" distinctly from "host." For example, claim 1 recites "a host bus adapter for the host" ( emphasis added) and "a volatile memory element coupled to the host bus adapter." By describing the host bus adapter as "for the host," the claim suggests the host bus adapter is not itself part of the "host," and by requiring the volatile memory element to be coupled "to the host bus adapter," the claim supports our conclusion that that a person of ordinary skill in the art would have understood that the "host" does not encompass the volatile memory element. Claim 14 recites explicitly "an input/ output bus coupled to the host computer and to a bus adapter" (emphasis added). If the "host" included the bus adapter, there would be no need for an input/output 7 Appeal2018-003534 Application 14/192, 683 bus to couple the two. Finally, claim 20 recites "a non-volatile memory element coupled [to the host computer] via a host bus adapter." By requiring the memory element be coupled to the host computer, the claim supports our conclusion that a person of ordinary skill in the art would have understood that the "host" does not encompass the non-volatile memory element or host bus adapter. In sum, we agree with Appellants that the Examiner's interpretation of "host" to encompass the recited "host bus adapter" and "volatile memory element" is unreasonable in light of the Specification and claims. The Examiner has erred in interpreting the claimed host as including the claimed host bus adapter and volatile memory element by reading the claimed host on the system of Hyde's hosts 210,220,225, network 260, and storage controller 240, by reading the claimed host bus adapter on Hyde's storage controller 240, and by reading the claimed volatile memory element on Hyde's cache 245. See supra 4, Examiner's findings. Accordingly, we do not sustain the anticipation rejection of independent claims 1, 14, and 20, or of dependent claims 2--4, 10, 15, and 17. Because the Examiner has not shown Blandy or Kline cures the deficiency noted above, we also do not sustain the obviousness rejections of dependent claims 5-9, 18, and 19 over Hyde and Blandy, or of dependent claims 11-13 and 16 over Hyde and Kline. 8 Appeal2018-003534 Application 14/192, 683 DECISION The Examiner's decision rejecting claims 1-20 is reversed. REVERSED 9