Ex Parte Pitzer

Patent Trial and Appeal Board

Dec 13, 2017

13768973 (P.T.A.B. Dec. 13, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/768,973 02/15/2013 Armin Pitzer KRAUP172US 8942
18052 7590 12/15/2017
Eschweiler & Potashnik, LLC
Rosetta Center
629 Euclid Ave., Suite 1000
Cleveland, OH 44114
EXAMINER
LEE, JAI M
ART UNIT PAPER NUMBER
2636
NOTIFICATION DATE DELIVERY MODE
12/15/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing @ eschweilerlaw. com
inteldocs_docketing @ cpaglobal. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ARMIN PITZER
(Applicant: LANTIQ DEUTSCHLAND GMBH)
Appeal 2017-003035
Application 13/768,9731
Technology Center 2600
Before JEAN R. HOMERE, BRUCE R. WINSOR, and
NABEEL U. KHAN, Administrative Patent Judges.
WINSOR, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the final rejection of
claims 1—22, which constitute all the claims pending in this application.
App. Br. 1. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
1 The real party in interest identified by Appellants is Lantiq Beteiligungs-
GmbH, a wholly owned company of Intel Corporation. App. Br. 2.
Appeal 2017-003035
Application 13/768,973
STATEMENT OF THE CASE
Appellant’s disclosed invention relates to “mitigate[ing] the effects of
an optical network unit (ONU) that is in a rogue state.” Spec. Abstract.
[PJassive optical networks (PON) provide in downstream
direction (network to user) a point to multipoint connection while
in upstream a point to point connection is used. A time division
multiplexing scheme is used for upstream transmission. Only
one defined optical network unit (ONU) is allowed to transmit
something at a pre-defmed timeslot. If one ONU is working in
an aberrant way the general upstream transmission system may
be disturbed. This ONU behavior is called Rogue ONU.
Spec. 115. Claim 1, which is illustrative, reads as follows:
1. An apparatus for mitigating effects of an optical
network unit (ONU) that is in a rogue state, the apparatus
comprising:
a main processor arranged as part of a monolithic
semiconductor chip, the main processor configured to process
signals from an optical telecommunication connection;
a laser driver that controls a laser coupled to the laser
driver; and
hardware logic arranged as part of the monolithic
semiconductor chip and arranged physically separate from the
main processor,
wherein the hardware logic independently effects the laser
driver to turn the laser off or reduce power output of the laser
significantly to mitigate the effects of the ONU in the rogue state.
The Examiner relies on the following prior art in rejecting the claims:
Nose et al. US 2012/0033963 Al Feb. 9, 2012
Aug. 28, 2012
Nov. 29, 2012
July 15, 2014
Mizutani et al. US 8,254, 780 B2
Davari et al. US 2012/0301134 Al
Lam et al. US 8,781,322 B2
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Application 13/768,973
Santiram Kal, Basic Electronics: Devices, Circuits and IT
Fundamentals 337 & 345 (2002) (hereinafter “Kal”).
The Examiner does not rely on the following references as prior art,
but refers to them for explanatory background information:
Kimetal. US 2012/0163808 A1 June 28, 2012
“Integrated circuit — Wikipedia the free encyclopedia,” Wikipedia
(last modified Sept 18, 2014) (accessed Sept. 18, 2014), current
version available at http://en.wikipedia.org/wiki/Integrated circuit.
M. Michael Vai, VLSI Design 1 (2001).
Claims 1, 5, 7, 8, 10, 11, 13—16, and 19-22 stand rejected under
35 U.S.C. § 103(a)2 as being unpatentable over Davari et al. (hereinafter
“Davari”) and Nose et al. (hereinafter “Nose”).3 See Final Act. 4—11.
Claims 2—\ and 18 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Davari, Nose, and Mizutani et al. (hereinafter
“Mizutani”). See Final Act. 11—13.
Claim 6 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Davari, Nose, and Fam et al. (hereinafter “Fam”). See
Final Act. 13—14.
Claims 9 and 12 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Davari, Nose, Fam, and Kal.3 See Final Act. 8, 14—15.
2 All rejections are under the provisions of 35 U.S.C. in effect prior to the
effective date of the Feahy-Smith America Invents Act of 2011 (“pre-AIA
first to invent”). Final Act 2.
3 Although listed and discussed by the Examiner as rejected over Davari and
Nose (see Final Act. 4, 8), claim 12 depends from claim 9 (see App. Br.
(Claims App’x) 9), which is rejected over Davari, Nose, Fam, and Kal (see
Final Act 14). Accordingly, we treat claim 12 as rejected over Davari, Nose,
Fam, and Kal. We consider the incorrect identification of the ground of
rejection of claim 12 to be a clerical or typographical error.
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Application 13/768,973
Claim 17 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Davari, Mizutani, and Lam. See Final Act 15—18.
Rather than repeat the arguments here, we refer to the Briefs (“App.
Br.” filed Apr. 8, 2016; “Reply Br.” Dec. 14, 2016) and the clean Substitute
Specification (“Spec.” filed Sept. 16, 2013, including the Drawings filed
Feb. 15, 2013, amended Sept. 16, 2013, and Abstract filed Feb. 15, 2013) for
the positions of Appellant and the Final Office Action (“Final Act.” mailed
Aug. 11, 2011) and Answer (“Ans.” mailed Oct. 14, 2016) for the reasoning,
findings, and conclusions of the Examiner. Only those arguments actually
made by Appellants have been considered in this decision. Arguments that
Appellants did not make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv) (2015).
ISSUES
The issues presented by Appellant’s arguments are as follows:
Does the Examiner err in finding the combination of Davari and Nose
teaches or suggests
hardware logic arranged as part of [a] monolithic semiconductor
chip and arranged physically separate from [a] main processor
[on the monolithic semiconductor chip], wherein the hardware
logic independently effects the laser driver to turn the laser off or
reduce power output of the laser significantly to mitigate the
effects of the ONU in the rogue state,
as recited in claim 1?
Does the Examiner err in finding the combination of Davari,
Mizutani, and Lam teaches or suggests
[an] ONU including a main processor arranged as part of a
monolithic semiconductor chip, . . . , the ONU further including
a laser driver on board the monolithic semiconductor chip that
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Application 13/768,973
controls a laser coupled to the laser driver, . . . receiving a
message signal indicating that the ONU is in [a] rogue state;
turning off the laser or reducing a power output of the laser
significantly using hardware logic independent of the main
processor in response to receiving the message signal indicating
that the ONU is in the rogue state,
as recited in claim 17?
ANALYSIS
Claim 1
In the Final Office Action, the Examiner finds Davari teaches
hardware logic on a monolithic semiconductor chip that is separate from a
main processor on the chip. Final Act. 5 (citing Davari | 345). The
Examiner relies on Nose’s emission force-quit controlling unit 6 to teach
that separate hardware logic includes hardware logic to turn the laser off or
to reduce the power output of the laser. Final Act. 5—6 (citing Nose Tflf 4, 73,
82, 88, 90, Figs. 1,6-1; Kim et al. 111).
Appellant contends that Davari’s disclosure of dedicated hardware
does not teach separate hardware logic (App. Br. 4); that Davari’s dedicated
hardware does not control the laser driver (App. Br. 4—5); and that Nose is
silent as to whether Nose’s emission force-quit controlling unit 6 is
implemented as hardware logic separate from a microprocessor (App. Br. 5).
We are persuaded of error by Appellant’s arguments.
Davari teaches that “packets are processed (for example) by a
microprocessor and some dedicated hardware, called NID[4] SoC[5] ....
Dedicated hardware, such as Encryption, ICV (Integrity Check Value), or
4 Network Identification or Interface Device. Davari 13.
5 System on a Chip. Id. 1 37.
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Application 13/768,973
CRC[6], could also exist in the SFP[7]-NID module.” Davari 1345.
Davari’s dedicated hardware performs logical functions and is described as
being in addition to, i.e., separate from a microprocessor. Therefore, we
agree with the Examiner that Davari’s dedicated hardware falls within the
broadest reasonable interpretation of “hardware logic arranged as part of [a]
monolithic semiconductor chip and arranged physically separate from [a]
main processor [on the monolithic semiconductor chip],” as recited in claim
1. See Ans. 18.
However, we agree with Appellant that neither Davari nor Nose
teaches or suggests using such separate hardware logic to “independently
effect[] the laser driver to turn the laser off or reduce power output of the
laser significantly to mitigate the effects of the ONU in the rogue state,” as
recited in claim 1. All of the hardware logic functions described in the
passage relied on by the Examiner are for packet processing (see Davari
1345) rather than controlling the laser driver. Although Davari does teach a
Tx_Disable control sent by the NID SoC to a laser driver (see Ans. 19
(citing Davari || 242, 345, Fig. 3)), the cited passages of Davari are silent as
to whether the Tx_Disable control is generated by the microprocessor of the
SoC or by dedicated hardware of the SoC (see id. 1345). We further
disagree with the Examiner’s explanation that because the “the main
function of [Davari’s] microprocessor is packet processing which involves
some dedicated hardware,” “it is logical to conclude that other dedicated
hardware exist that perform functions not related to packet processing.”
App. Br. 19. Given the well-known versatility of microprocessors, the fact
6 Cyclic Redundancy Check. Id. 139.
7 Short Form factor Pluggable. Id. 14.
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Application 13/768,973
that a microprocessor performs packet processing does not lead reasonably
to any conclusion that it does or does not perform other functions.
Similarly, we agree with Appellant that Nose’s Figure 1 is a
functional diagram of an ONU 1, and is silent as to the physical
implementation of the functional items 2—8. App. Br. 5 (citing Nose 135
(“FIG. 1 is a diagram of an exemplary functional configuration of an optical
subscriber terminating device (hereinafter, an ‘Optical Network Unit
(ONU)’) according to an aspect of the present invention.”)); accord Nose
113. Even accepting, arguendo, the Examiner’s explanation that one of
ordinary skill in the art would have understood that optical transmitting and
receiving unit 2 (Nose 136, Fig. 1) is implemented as separate hardware
(Ans. 20), one cannot reasonably draw any inference from that
understanding as to whether Nose’s functional items 3—8 (Fig. 1), and in
particular the emission force-quit controlling unit 6 and emission force-quit
unit 7, are implemented in a microprocessor or in separate hardware logic.
Appellant has persuaded us of error in the rejection of claim 1.
Accordingly, we do not sustain the rejection of claim 1 or claims 2—16 and
18—22, which depend, directly or indirectly, from claim 1. See In re Fine,
837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious
under section 103 if the independent claims from which they depend are
nonobvious.”)
Claim 17
Claim 17 is rejected over a combination of Davari, Mizutani, and
Lam. See Final Act 15—18. Appellant argues the patentability of claim 17
as if it were rejected over Davari, Nose, and Mizutani, making no mention of
the Examiner’s reliance on Lam. See App. Br. 5—6. In particular, Appellant
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argues “[Mizutani’s] power management unit 18310 referred to on page 17
of the Final Office Action is clearly no hardware logic monolithically
integrated with the main processor but separate therefrom, as claimed (see
Fig. 14 of Mizutani).” Id. However, Appellant does not address the
Examiner’s reliance on Lam to teach a laser driver on board a monolithic
semiconductor chip. See Final Act. 18 (citing Lam col. 8,11. 35—41).
Because Appellant’s arguments are not commensurate with the
articulated ground of rejection, they do not demonstrate error in the rejection
of claim 17. Accordingly, we sustain the rejection of claim 17.
DECISION
The decision of the Examiner to reject claim 17 is affirmed.
The decision of the Examiner to reject claims 1—16 and 18—22 is
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§§ 41.50(f), 41.52(b).
AFFIRMED-IN-PART
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