Ex Parte Ping et al

Patent Trial and Appeal BoardDec 29, 2016

13407855 (P.T.A.B. Dec. 29, 2016)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/407,855 02/29/2012 Er-Xuan PING 06059-US-DIV5 5426 68256 7590 01/03/2017 Ponversiant Tntelleetnal Prnnertv Management Tne EXAMINER 5601 Granite Parkway Suite 1300 MAI, ANH D Plano, TX 75024 ART UNIT PAPER NUMBER 2829 NOTIFICATION DATE DELIVERY MODE 01/03/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipadmin @ conversantip. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ER-XUAN PING and JEFFREY A. MCKEE Appeal 2014-009897 Application 13/407,855 Technology Center 2800 Before: MARC S. HOFF, CARLA M. KRIVAK, and ELENI MANTIS MERCADER, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL Appeal 2014-009897 Application 13/407,855 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1— 11. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. THE INVENTION The claimed invention is directed to a vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain. Abstract. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A vertical transistor structure extending in a direction substantially normal to a semiconductive region of a substrate, comprising: a vertical transistor gate region oriented in a vertical plane from the substrate surface, including at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface defining a facet; a vertical transistor source including a diffusion region adjacent to said transistor gate region within the semiconductive region; and a vertical transistor drain including a diffusion region adjacent to said transistor gate region within the semiconductive region. REFERENCE The prior art relied upon by the Examiner in rejecting the claims on appeal is: Yoshida US 5,599,724 Feb. 4, 1997 2 Appeal 2014-009897 Application 13/407,855 REJECTIONS The Examiner made the following rejections: Claim 1 stands rejected under 35 U.S.C. § 112, first paragraph, as failing to comply with the enablement requirement. Final Act. 6—7. Claims 1—11 stand rejected under 35 U.S.C. §112, second paragraph, as being indefinite. Final Act. 7—9. Claims 1—11 stand rejected under 35 U.S.C. § 101 because the disclosed invention is inoperative and lacks utility. Final Act. 4—6. Claims 1—11 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Yoshida as evidenced by Matsumoto. Final Act. 9—12. ANAFYSIS Claims 1 stands rejected under 35 U.S.C. 112, first paragraph, as failing to comply with the enablement requirement We are persuaded by Appellants’ argument that the Examiner has confused a generalized vertical transistor structure with a specific vertical transistor itself. We further agree with Appellants that the transistor structure is sufficiently described in the specification to enable a person of ordinary skill in the art to make and use the inventive vertical transistor structure as a working vertical transistor (Br. 6). Accordingly, we do not sustain the Examiner’s rejection of claim 1. Claims 1—11 stand rejected under 35 U.S.C. 112, second paragraph Contrary to the Examiners’ finding that claim 1 is indefinite [cite], we agree with Appellants that the claim is definite as explained in the Brief (see Br. 7). We agree with Appellants that one skilled in the art at the time of the invention would understand the semiconductor surface (see 10" in Figure 3 Appeal 2014-009897 Application 13/407,855 3C) as not being the semiconductive region (Br. 7). Rather, the semiconductive region is the source region, gate region, and drain region, which are semiconductive in that they are subject to a potential providing an electric field in the gate region (Br. 7). Accordingly, we do not sustain the Examiner’s rejection of claims 1— 11. Claims 1-11 stand rejected under 35 U.S.C. 101 As stated above, we are persuaded by Appellants’ argument that the Examiner has confused a generalized vertical transistor structure with a specific vertical transistor itself. Further, the transistor structure is sufficiently described in Appellants’ Specification to enable a person having ordinary skill in the art to make and use the inventive vertical transistor structure as a working vertical transistor (Br. 4—5). Accordingly, we reverse the Examiner’s rejection of claims 1—11. Claims 1 11 stand rejected under 35 U.S.C. 102(b) Appellants argue, inter alia, that Yoshida as evidenced by Matsumoto do not disclose “a vertical transistor gate region oriented in a vertical plane from the substrate surface, including at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface defining a facet” as recited in claim 1 (see Br. 7—12). We are persuaded by Appellants’ argument. Appellants contend that claim 1 requires at least two overlying layers and each of the layers includes a top or upper surface defining a facet. Thus, there are at least two facets required (Br. 7). We agree with Appellants that, contrary to the Examiner’s assertions, Yoshida’s portions 11—1, 11—2, 11—3 are portions of the epitaxial 4 Appeal 2014-009897 Application 13/407,855 layer and they do not constitute different epitaxial layers: that is, “Yoshida never refers to the channel region 11 as being formed of ‘layers’” (Br. 8). We further disagree with the Examiner’s finding that Matsumoto shows the inherent formation of a facet on top of an SEG layer (Ans. 9). The Examiner refers to the two different portions 4 and 6 of Matsumoto as constituting a single SEG layer, and facet 7 as being the facet, and Yoshida’s portions 11— 1, 11—2, and 11—3 as layers, as opposed to different portions (see Final Act. 10). The Examiner’s position that the combined portions 4 and 6 of Matsumoto constitute a single layer contradicts the Examiner’s position that each of the different portions of the Yoshida constitute a single layer. If Yoshida’s portions 11—1, 11—2, and 11—3 constitute layers then Matsumoto’s portions 4 and 6 must also be considered layers. If this is accurate, then there is only one facet 7 for both layers 4 and 6—not two facets. Neither Yoshida nor Matsumoto discloses more than one facet as claimed (“at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface defining a facet”). Accordingly, we reverse the Examiner’s rejection of claim 1 and for the same reasons the Examiner’s rejection of claims 2—11. DECISION For the above reasons, the Examiner’s rejection of claims 1—11 is reversed. No time period for taking any subsequent action in connection with this appeal maybe extended under 37 C.F.R. § 1.136(a)(l)(iv) (2009). REVERSED 5