Ex Parte Patel et al

Patent Trial and Appeal BoardDec 7, 2012

11564563 (P.T.A.B. Dec. 7, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte PIYUSH CHUNILAL PATEL and DEEPAK K. SINGH ____________ Appeal 2010-004147 Application 11/564,563 Technology Center 2100 ____________ Before DENISE M. POTHIER, JUSTIN T. ARBES, and JENNIFER S. BISK, Administrative Patent Judges. POTHIER, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1-20. Claim 21 has been objected to but would otherwise be allowable if rewritten in independent form to include all limitations of its Appeal 2010-004147 Application 11/564,563 2 base claim and any intervening claims. Br. 4; Final Rej. 6.1 We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. Invention Appellants’ invention relates to a technique for saving bus switching power and reducing noise. See Abstract. Illustrative claims 1 and 6 are reproduced below with a certain disputed limitation emphasized: 1. A computer implemented method for saving a bus switching power and reducing a noise, the computer implemented method comprising: receiving, at a first cache, a request for data from a requestor; determining if the data is stored on the first cache; responsive to determining that the data is stored on the first cache, identifying a bus in a plurality of buses on which to return the data to form an identified bus; sending the data to the requestor on the identified bus; and initiating a logical state on a remaining plurality of buses stemming from the first cache in order to save the bus switching power and reduce the noise. 6. The computer implemented method of claim 1, wherein the logical state is initiated from a control circuit in the first cache. The Rejections The Examiner relies on the following as evidence of unpatentability: Heil US 5,528,764 June 18, 1996 Peir US 7,076,613 B2 July 11, 2006 Bockhaus US 2006/0179175 A1 Aug. 10, 2006 1 Throughout this opinion, we refer to (1) the Final Rejection mailed March 12, 2009; (2) the Appeal Brief filed August 6, 2009; and (3) the Examiner’s Answer mailed November 4, 2009. Appeal 2010-004147 Application 11/564,563 3 Claims 1, 2, 5-9, 12-15, and 18-20 are rejected under 35 U.S.C. § 103(a) as unpatentable over Bockhaus and Heil. Ans. 3-6. Claims 3, 4, 10, 11, 16, and 17 are rejected under 35 U.S.C. § 103(a) as unpatentable over Bockhaus, Heil, and Peir. Ans. 6-7. THE OBVIOUSNESS REJECTION OVER BOCKHAUS AND HEIL Regarding illustrative claim 1, Appellants argue that Bockhaus and Heil collectively fail to teach initiating a logical state on the remaining buses stemming from the first cache. Br. 15. Appellants assert that Heil has only one bus, and thus Heil fails to teach multiple buses stemming from the first cache as recited. See Br. 18-20. Appellants also contend the Examiner has not provided a sufficient reason for combining the cited references. Br. 21. As for claim 6, Appellants argue among other things that Bockhaus and Heil collectively fail to teach that the logical state is initiated from a control circuit in the first cache. Br. 22, 26. Specifically, Appellants contend that the bus in Heil is not driven by a cache – rather a master device and central arbiter device – and thus does not teach that the logical state is initiated from the recited first cache. Br. 23. Appellants also assert that Bockhaus does not cure this deficiency in Heil. Br. 26. ISSUES (1) Under § 103, has the Examiner erred by finding that Bockhaus and Heil collectively would have taught or suggested: (a) initiating a logical state on a remaining plurality of buses stemming from the first cache as recited in claim 1? Appeal 2010-004147 Application 11/564,563 4 (b) the logical state is initiated from a control circuit in the first cache as recited in claim 6? (2) Is the Examiner’s reason to combine Bockhaus and Heil supported by articulated reasoning with some rational underpinning to justify the Examiner’s obviousness conclusion? ANALYSIS Based on the record before us, we find no error in the Examiner’s rejection of illustrative claim 1, which calls for initiating a logical state on a remaining plurality of buses stemming from the first cache. The Examiner relies on Bockhaus to teach the recited multiple buses stemming from a first cache. See Ans. 3 (discussing items 240, 113 in Figure 2), 8 (“the Bockhaus reference was used to teach the claimed feature of a plurality of buses stemming from the first cache”). Thus, Appellants’ contention that Heil fails to teach multiple buses stemming from a cache (Br. 18) is misplaced. The Examiner, however, turns to Heil as teaching initiating a logical state on a bus and respective byte lanes of a bus that are not being used to transfer data. See Ans. 4, 8-9. Heil teaches transmitting Address and Data (AD) signals on the unused bus portions and during idle time with stable values or data, such as transmitting the same data from a previous bus phase. Heil, col. 7, ll. 17-18, 21-33 (cited at Ans. 4, 8). Each of these sent stable values represents a given state of an unused bus portion. Heil also explains that an AD signal is made up of either a 32-bit target device address or 4 bytes of data. Heil, col. 4, ll. 51-55. These cumulative teachings in Heil at a minimum suggest to an ordinary artisan transmitting or initiating a logical state on any bus not being used in a bus system (e.g., sending a 4-byte data Appeal 2010-004147 Application 11/564,563 5 value on the bus) so as to minimize bus switching power consumption in a system. See Heil, col. 4, ll. 51-55; col. 7, ll. 21-33. Given these teachings in Heil, an ordinarily skilled artisan would have recognized that including such a teaching in Bockhaus’ system having multiple buses stemming from a first cache (Ans. 3) would equally improve Bockhaus’ system in a similar manner by minimizing bus switching power consumption. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Such a combination also predictably yields no more than one would expect from such a combination – placing unused bus portions and thus buses, including those stemming from the first cache, in a logical state in order to save power as recited. See id. at 416. Given that Heil supports using this technique to minimize bus switching power consumption (see col. 7, ll. 28- 31) and Bockhaus can benefit from such a process, the Examiner has also provided a reason (e.g., minimizing power consumption) for combining such references with some rational underpinning to support the Examiner’s obviousness conclusion. See Ans. 4, 8. Also, Peir was not cited to reject claim 1 (see Ans. 3-4), and we need not address whether Peir cures any alleged deficiency. Br. 21. Additionally, the Examiner explains that Heil’s byte lanes are equivalent to the claimed “plurality of buses” and therefore Heil teaches initiating a logical state on the remaining buses as recited. Ans. 9. Appellants have not filed a Reply Brief, and this finding by the Examiner remains undisputed. Based on this undisputed position, the record further demonstrates that Heil teaches the recited initiating a logical state on the remaining buses. Moreover, while Heil teaches that the in-line cache may be serviced without having to propagate the access to the Peripheral Appeal 2010-004147 Application 11/564,563 6 Component Interconnect (PCI) bus (see Br. 20), the Examiner has not relied upon Heil for the cache feature. We therefore are not persuaded by Appellants’ argument (Br. 20) that Heil, alone or in combination with Bockhaus, fails to teach initiating a logical state on the remaining buses stemming from the first cache as claimed or that the Examiner’s reason for combining the cited references is conclusory. For the foregoing reasons, Appellants have not persuaded us of error in the rejection of independent claim 1 and claims 2, 5, 7-9, 12-15, 18, and 20 not separately argued with particularity (Br. 11-26). Claims 6 and 19 Based on the record before us, we find error in the Examiner’s rejection of illustrative claim 6, which calls for the logical state being initiated from a control circuit in the first cache. As stated above, the Examiner finds that Heil teaches initiating a logical state on a bus (Ans. 4, 8- 9) and additionally finds that “a device” attached to a bus initiates this logical state (Ans. 10). The Examiner concludes that an ordinarily skilled artisan would have recognized that there must be some control circuit on this device to initiate the logical state, and therefore the cited references teach the claimed limitation. Ans. 10. Even assuming that the skilled artisan would have known to include such a control circuit on a device, the Examiner has not demonstrated that one skilled in the art would have recognized that this “device,” based on the teachings of Heil and Bockhaus, would be the first cache. See Ans. 4, 8-10. Also, Appellants have provided some evidence to the contrary showing that Heil teaches or suggests using a master device and arbiter device to initiate Appeal 2010-004147 Application 11/564,563 7 any logical state. Br. 23. The Examiner discusses, in response, that Bockhaus includes a first cache (Ans. 5, 10) and Heil suggests a device that includes a control circuit (Ans. 10). This, however, does not adequately demonstrate that an ordinary skilled artisan would have recognized using the cache’s control circuit in Bockhaus to initiate such a function. See id. Put another way, the Examiner has not adequately articulated a reason with some rational underpinning for using Bockhaus’ first cache’s control circuit to initiate the logical states on the bus. Thus, on balance and based on the record, we are persuaded by Appellants’ arguments. For the foregoing reasons, Appellants have persuaded us of error in the rejection of claim 6 and claim 19, which recites commensurate limitations. THE REMAINING REJECTION The Examiner finds that Bockhaus, Heil, and Peir teach all the limitations in claims 3, 4, 10, 11, 16 and 17. Ans. 6-7. For this rejection, Appellants refer to the dependency of these claims to claims 1, 8, and 15 and the previous arguments of claim 1. Br. 27. The issues before us, then, are the same as those in connection with claim 1, and we refer Appellants to our previous discussion. For the reasons stated previously, Appellants have not persuaded us of error in the rejection of claims 3, 4, 10, 11, 16, and 17. CONCLUSION Under § 103, the Examiner erred in rejecting claims 6 and 19 but did not err in rejecting claims 1-5, 7-18, and 20. Appeal 2010-004147 Application 11/564,563 8 DECISION The Examiner’s decision rejecting claims 1-20 is affirmed-in-part. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED-IN-PART babc