Ex Parte Patel et al

Patent Trial and Appeal Board

Nov 30, 2012

11267627 (P.T.A.B. Nov. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
___________
Ex parte JAGRUT VILISKUMAR PATEL, GREGORY BULLARD, and
SANAT KAPOOR
___________
Appeal 2010-007918
Application 11/267,627
Technology Center 2800
__________

Before MARC S. HOFF, CARLA M. KRIVAK,
and ELENI MANTIS MERCADER, Administrative Patent Judges.

MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-35. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
THE INVENTION
Appellants’ claimed invention is directed to a system and technique
for calibrating an integrated circuit to an electronic component (see Spec. 1).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal.
1. An electronic device, comprising:
an electronic component; and
an integrated circuit configured to generate a system clock and
an external clock having a programmable delay from the system
clock, the integrated circuit being further configured to provide the
external clock to the electronic component, determine a delay range
between system clock and the external clock in which the integrated
circuit and the electronic component can communicate, and program
the external clock with one of a plurality of predetermined delay
values based on the delay range.
REFERENCES and REJECTIONS
The Examiner objected to the Specification for failing to provide
antecedent basis for the limitation of: “determine a delay range between
system clock and the external clock in which the integrated circuit and the
electronic component can communicate, and program the frequency of the
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system clock based on the delay range” as allegedly recited in claims 1, 12
and 23.
The Examiner rejected claims 1-35 under 35 U.S.C. § 112, first
paragraph, for allegedly failing to comply with the enablement requirement.
The Examiner rejected claims 1, 3, 4, 11, 12, 14, 15, 22, 23, 25, 26,
and 33 under 35 U.S.C. § 102(b) based on the teachings of Fischer (US
Patent No. 5,920,216, issued July 6, 1999).
The Examiner rejected claims 34 and 35 under 35 U.S.C. § 103(a)
based on the teachings of Zorian et al. (US Patent No. 7,290,186 B1; issued
Oct. 30, 2007).
ISSUES
The issues are whether the Examiner erred in finding that:
1. Claims 1-35 are not enabled under 35 U.S.C. § 112, first
paragraph, for the claim limitation of: “determin[ing] a delay range between
system clock and the external clock in which the integrated circuit and the
electronic component can communicate, and program[ing] the external clock
with one of a plurality of predetermined delay values based on the delay”;
2. Fisher teaches an integrated circuit that determines a delay range
between the system clock and the external clock in which the integrated
circuit and the electronic component can communicate as recited in
independent claims 1, 12, and 23; and
3. Claims34 and 35 are unpatentable over Zorian.

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PRINCIPLES OF LAW
The standard for determining whether the Specification meets the
enablement requirement is whether a person skilled in the art can make and
use the claimed invention without undue experimentation. In re Wands,
858 F.2d 731, 737 (Fed. Cir. 1988).
The claims, of course, do not stand alone. Rather, they are part
of “a fully integrated written instrument” . . . consisting
principally of a specification that concludes with the claims.
For that reason, claims “must be read in view of the
specification, of which they are a part.” . . . . [T]he
specification “is always highly relevant to the claim
construction analysis. Usually, it is dispositive; it is the single
best guide to the meaning of a disputed term.”
Phillips v. AWH Corp., 415 F.3d 1303, 1315 (Fed. Cir. 2005).
ANALYSIS
The Specification is objected to under 35 C.F.R. § 1.75(d)(1),as failing to
provide antecedent basis for claim terminology
The Examiner objected to the Specification for failing to provide
antecedent basis for the limitation of: “determine a delay range between
system clock and the external clock in which the integrated circuit and the
electronic component can communicate, and program the frequency of the
system clock based on the delay range” as allegedly recited in claims 1, 12
and 23 (Ans. 6). We note that there is no such claim limitation in claims 1,
12, and 23. Rather, claim 1, recites: “determine a delay range between
system clock and the external clock in which the integrated circuit and the
electronic component can communicate, and program the external clock
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with one of a plurality of predetermined delay values based on the delay
range” (emphasis added). Similar limitations are recited in claims 12 and
23.
Regardless, an objection to the Specification is a petitionable matter
under 37 C.F.R. § 181 to the Director of the USPTO. See MPEP 706.01: the
“Board will not hear or decide issues pertaining to objections and formal
matters which are not properly before the Board.” Accordingly, we will not
decide the objection.

Claims 1-35 are rejected under 35 U.S.C. § 112, first paragraph,
as failing to comply with the enablement requirement

Appellants argue that the Specification provides adequate enablement
for the limitation of: “determine a delay range between system clock and the
external clock in which the integrated circuit and the electronic component
can communicate, and program the external clock with one of a plurality of
predetermined delay values based on the delay range” as recited in claim 1
and similarly recited in independent claims 12, 23, and 34 is not supported
by the Specification (App. Br. 11-12).
Appellants explain that the delay range is determined during a
characterization process by a calibration algorithm programmed into the
integrated circuit, as recited in the Specification (App. Br. 12; ¶ [0038]).
While the characterization process is discussed with respect to the system
clock and the feedback clock delay (¶ [0038]), the Specification discloses
that the process could also be performed for the external clock delay (App.
Br. 12; Spec. ¶¶ [0044]-[0045]).
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The Examiner’s contention that the Specification only discloses the
function but not the structure of the controller 113 does not take into account
the functional block diagram of the controller 113 shown in Figure 4, and
the respective description set forth in the Specification (see Ans. 7-8, Spec.
¶¶ [0030]-[0038]). We agree with Appellants, that sufficient detail is
provided in the Specification regarding the structure of the controller 113 for
a person of ordinary skill in the art to determine the delay range between the
system clock and the external clock without undue experimentation (App.
Br. 12; Spec. ¶¶ [0030]-[0031]). See Wands, 858 F.2d at 737.
Accordingly, we reverse the Examiner’s rejection of claims 1-35 for
lack of enablement.
Claims 1, 3, 4, 11, 12, 14, 15, 22, 23, 25, 26, and 33
Appellants argue that Fischer does not teach an integrated circuit
which “determine[s] a delay range between system clock and the external
clock in which the integrated circuit and the electronic component can
communicate” as recited in claim 1 (App. Br. 15). The Examiner contends
that Fischer teaches a “delay range” between clock signals A, B and/or X is
calculated by the elements 18 through 42 for supporting communication,
such as a synchronization of these clocks, between an integrated circuit (12-
16) and an electronic component (see Ans. 8; col. 4, ll. 36-59).
Appellants explain that Fischer teaches the determination of a specific
delay to eliminate phase error between clocks A and B (App. Br. 15).
Fischer does not find a delay range inclusive of any delay “in which the
integrated circuit and the electronic component can communicate” (see App.
Br. 15-16; col. 4, ll. 1-10). As reiterated by the Appellants, one particular
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delay value is not a range (Reply Br. 3). Thus, the determinative issue is
whether “delay range” can be a single specific delay value or whether it
requires more than one delay value.
We turn to Appellants’ Specification for the meaning of the term
“delay range” because the Specification is the single best guide to the
meaning of a disputed term. See Phillips, 415 F.3d at 1315. Appellants’
Specification defines the range as being a “continuous range bound by a
‘maximum delay’ set by the minimum resampling set-up time tset-up time of
the controller 113 and a ‘minimum delay’ set by the minimum set up time
tset-up of the SDRAM 118” (Spec. ¶ [0038]). Accordingly, the terms “delay
range” must be interpreted as a continuous range that is bound by a
maximum and a minimum value. Thus, the Examiner’s interpretation of a
single delay value does not meet the claim limitation of a “delay range.”
Accordingly, we reverse the Examiner’s rejection of claim 1 and for
the same reasons the rejections of claims 3, 4, 11, 12, 14, 15, 22, 23, 25, 26,
and 33 under 35 U.S.C. §102(b).
Claims 34-35
Appellants have not presented any arguments regarding the rejection
of claims 34 and 35 over Zorian. Accordingly, we pro forma affirm these
rejections.
CONCLUSIONS
The Examiner erred in rejecting claims 1-35 under 35 U.S.C. § 112,
first paragraph, for allegedly failing to comply with the enablement
requirement.
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The Examiner erred in rejecting claims 1, 3, 4, 11, 12, 14, 15, 22, 23,
25, 26, and 33 under 35 U.S.C. § 102(b) based on the teachings of Fischer.
The rejections of claims 33 and 34 are pro forma affirmed.
DECISION
The Examiner’s decision rejecting claims 1-35 under 35 U.S.C. § 112,
first paragraph is reversed. The Examiner’s decision rejecting claims 1, 3, 4,
11, 12, 14, 15, 22, 23, 25, 26, and 33 under 35 U.S.C. § 102(b) is reversed.
The Examiner’s decision rejecting claims 34 and 35 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010).
AFFIRMED-IN-PART

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