Ex Parte ParkinsonDownload PDFPatent Trial and Appeal BoardMar 28, 201812626988 (P.T.A.B. Mar. 28, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 12/626,988 11130/2009 Ward Parkinson 141308 7590 03/28/2018 Global IP Law Group, LLC 55 W. Monroe Street Suite 3400 Chicago, IL 60603 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. OVX-32 3238 EXAMINER HUANG, MIN ART UNIT PAPER NUMBER 2827 MAILDATE DELIVERY MODE 03/28/2018 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte WARD PARKINS ON Appeal2017-003729 Application 12/626,988 Technology Center 2800 Before ROMULO H. DELMENDO, GEORGE C. BEST, and DONNA M. PRAISS, Administrative Patent Judges. BEST, Administrative Patent Judge. DECISION ON APPEAL The Examiner has finally rejected claims 1-19 of Application 12/626,988. Final Act. (December 22, 2015). Appellant 1 seeks reversal of these rejections pursuant to 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6. For the reasons set forth below, we affirm. 1 Carlow Innovations LLC is identified as the real party in interest. Appeal Br. 3. Since the filing of the Appeal Brief, Appellant has reported that Carlow Innovations LLC assigned its interest to Ovonyx Memory Technology, LLC. Statement Under 37 C.F.R. § 3.73(b) (August 25, 2016). Appeal2017-003729 Application 12/626,988 BACKGROUND The '988 Application describes integrated circuit memory devices comprised of non-volatile memory elements, input/ output circuitry, and mode control circuitry. Spec. 3. The mode control circuitry allows the memory device to adapt to any one of a plurality of integrated circuit memory interfaces. Id. Claims 1 and 12 are representative of the '988 Application's claims and are reproduced below from the Claims Appendix: 1. An apparatus, comprising: a memory array, said memory array including a nonvolatile memory element; input/output circuitry, set input/output circuitry configured to operate said nonvolatile memory element in each of a plurality of selectable modes of memory operation; and control circuitry, said control circuitry configured to control set input/output circuitry to operate said nonvolatile memory element in a first of said selectable modes of memory operation, said control circuitry further configured to control said input/output circuitry to reconfigure said nonvolatile memory element from said first of said selectable modes of memory operation to a second of said selectable modes of memory operation. Appeal Br. 26. 12. An electronic system comprising: a memory array, said memory array including a phase- change memory element; input/ output circuitry configured to operate said phase- change memory element in each of a plurality of selectable modes of memory operation; mode control circuitry configured to modify a signal path through said input/output circuitry to select one of said plurality of selectable modes; and 2 Appeal2017-003729 Application 12/626,988 controller circuitry configured to access the phase-change memory element. Appeal Br. 27-28. REJECTIONS On appeal, the Examiner maintains the following rejections: 1. Claims 1, 7, 8, 11, and 17-19 are rejected under 35 U.S.C. § 102(e) as anticipated by Norman '542. 2 Final Act. 4. 2. Claims 2, 9, and 12 are rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Norman '542 and Lee. 3 Final Act. 5. 3. Claims 13, 15, and 16 are rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Norman '542, Lee, and Norman '757. 4 Final Act. 7. 4. Claims 3-6 and 10 are rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Norman '542, Lee, and Nazarian. 5 Final Act. 7. 5. Claim 14 is rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Norman '542, Lee, Norman '757, and Herrod. 6 Final Act. 8. 2 US 2011/0035542 Al, published February 10, 2011. 3 US 2007/0295949 Al, published December 27, 2007. 4 US 2009/0063757 Al, published March 5, 2009. 5 US 6,977,842 B2, issued December 20, 2005. 6 US 2010/0333166 Al, published December 30, 2010. 3 Appeal2017-003729 Application 12/626,988 DISCUSSION On September 8, 2015, we decided an earlier appeal in the '988 Application. See Ex parte Parkinson, No. 2013-008762, 2015 WL 5578695 (PTAB September 8, 2015). In that appeal, we affirmed the Examiner's rejection of claims 1-19. Appellant responded by filing a Request for Continued Examination. Request for Continued Examination Under 3 7 CPR 1.114 (November 11, 2015). In the RCE, Appellant did not amend any of claims 1-19. RCE 2-5. On December 22, 2015, the Examiner issued a Final Rejection, stating: The applicant's argument is basically the same as that presented before in the appeal to the Appeal Brief [sic] dated 2/24/2013, with one additional argument that prior art Norman (PGPUB 20110035542), hereinafter Norman, teaches ""the different memory patent needs of a system" by partitioning the memory in two different blocks, each of which is dedicated to a different and unvarying type of memory and controlled by different and unvarying control block". The main reference mentioned by the applicant is based on Fig 5 of Norman and related text. Final Act. 2-3. Appellant now seeks review of the Final Action. For the following reasons, we affirm the rejection of claims 1-19 of the '988 Application. There are two independent claims before us on appeal: claim 1 and claim 12. Appellant presents detailed arguments for reversal of the rejection of claim 1 as anticipated by Norman '542. Appeal Br. 14--21. With respect to claim 12, Appellant reiterates the arguments made with respect to claim 1. Id. at 22 ("Based on the remarks hereinabove, Applicant maintains that Norman fails to disclose reconfigurability of memory elements and fails to disclose input/output circuitry configured to operate a particular memory 4 Appeal2017-003729 Application 12/626,988 element in multiple modes of operation."). Furthermore, with respect to each of the dependent claims on appeal, Appellant relies upon the arguments presented for reversal of the respective parent independent claim. See, e.g., id. at 23. Accordingly, we select claim 1 as representative of the claims on appeal. The remaining claims will stand or fall with claim 1. 37 C.F.R. § 41.37(c)(l)(iv). Appellant's Reply Brief summarizes the basis for Appellant's appeal: Applicant submits that the difference in position between Applicant and the Examiner rest on the construction of the term "dynamically allocated" in the Norman reference (US20110035542Al). The Examiner maintains that by "dynamically allocated", Norman discloses any particular memory block can be reconfigured for one memory type (e.g. SRAM) to another memory type (e.g. DRAM) and that Norman thus reads on Applicant's claim 1. Applicant, in contrast, maintains that each memory block of Norman is dedicated to a single type of memory and that while multiple types of memory may be present in different memory blocks within an array, none of the individual memory blocks can be reconfigured from one memory type to a different memory type. Applicant accordingly maintains that none of the memory blocks of Norman is reconfigurable as required by Applicant's claim 1. Applicant maintains that the type of memory associated with each of Norman's memory blocks is invariant. Applicant respectfully submits that Norman's disclosure of "dynamically allocated" means not that the type of memory associated with a particular memory block can be reconfigured, but rather that the size (e.g. storage capacity in MB) of a memory block of invariant type can be adjusted at the time of access according to the memory needs of an operation currently under execution. Applicant maintains that Norman's reference to "dynamically allocated" occurs only with respect to storage capacity of a particular memory type and not to replacement of 5 Appeal2017-003729 Application 12/626,988 one type of memory functionality with another type of memory functionality. Reply Br. 2-3 (emphasis added). After reviewing the briefs and Norman '542, we remain unpersuaded of the existence of reversible error by Appellant's argument. Norman '542 summarizes its disclosure as follows: To satisfy the various memory type needs of a system, a multiple-type memory is partitioned into separate memory blocks that are configured to emulate the various memory types. As discussed above, the memory blocks of the multiple- type memory can be dynamically allocated. Accordingly, in addition to meeting the different memory type needs of a system, the multiple-type memory can also meet and adapt to the changing memory requirements of a system. Norman '542 i-f 41. In the memory device of Norman '542, each memory block is associated with a control logic block that specifies which type of memory the combination of the control logic block and memory block will emulate. See Norman '542 i-fi-125-34; Figs. 2--4. In use, the memory size of the memory type can be adjusted by dynamically allocating one or more memory blocks to a memory type by changing the control logic block associated with that memory block. Id. i-fi-135-36. Thus, Norman '542's dynamic allocation process changes the type of memory functionality performed by each memory block that is dynamically allocated from one control logic block to another. See also Ans. 3. CONCLUSION For the reasons set forth above, we affirm the rejection of claims 1-19 of the '988 Application. 6 Appeal2017-003729 Application 12/626,988 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED 7 Copy with citationCopy as parenthetical citation