Ex Parte Oikawa et al

Patent Trial and Appeal BoardAug 27, 2014

12423563 (P.T.A.B. Aug. 27, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/423,563 04/14/2009 Yoshiaki Oikawa 0553-0745 8766 24628 7590 08/27/2014 Husch Blackwell LLP Husch Blackwell Sanders LLP Welsh & Katz 120 S RIVERSIDE PLAZA 22ND FLOOR CHICAGO, IL 60606 EXAMINER ENAD, CHRISTINE A ART UNIT PAPER NUMBER 2823 MAIL DATE DELIVERY MODE 08/27/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte YOSHIAKI OIKAWA, MASAYUKI KAJIWARA, MASATAKA NAKADA, MASAMI JINTYOU, and SHUNPEI YAMAZAKI ____________ Appeal 2012-004057 Application 12/423,5631 Technology Center 2800 ____________ Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. HOUSEL, Administrative Patent Judge. DECISION ON APPEAL Appellants seek our review under 35 U.S.C. § 134 of the Examiner’s decision finally rejecting claims 11–20. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). We REVERSE.2 1 According to Appellants, the Real Party in Interest is Semiconductor Energy Laboratory Co., Ltd. (Appeal Br. 4). 2 Our decision refers to Appellants’ Appeal Brief (Appeal Br.) filed October 3, 2011, the Examiner’s Answer (Ans.) mailed November 7, 2011, and Appellants’ Reply Brief (Reply Br.) filed January 9, 2012. Appeal 2012-004057 Application 12/423,563 2 STATEMENT OF THE CASE The invention is directed to a method for manufacturing a semiconductor device with improved reliability by reducing the degree of peeling of a film. Spec. ¶ [0006]. Representative independent claim 11, reproduced below, is illustrative of the invention: 11. A method for manufacturing a semiconductor device, comprising steps of: forming a first inorganic insulating layer over a substrate; forming a semiconductor element layer including a transistor over the first inorganic insulating layer; forming a first opening portion in the semiconductor element layer; forming a second inorganic insulating layer over the semiconductor element layer and a surface of the first inorganic insulating layer exposed by the first opening portion; forming an organic insulating layer over the semiconductor element layer with the second inorganic insulating layer interposed therebetween; forming a second opening portion in the organic insulating layer, forming a plurality of opening portions in parts of the second inorganic insulating layer, which are exposed by the second opening portion; and forming a third inorganic insulating layer over the plurality of opening portions and the organic insulating layer. Claims App’x, Appeal Br. 17. Claim 15, the remaining independent claim before us, similarly recites a method of manufacturing a semiconductor device as in claim 11 above, with additional steps of forming a separation layer between the substrate and the first inorganic insulating layer, forming a sealing layer over the third inorganic insulating layer, separating the substrate and separation layer, Appeal 2012-004057 Application 12/423,563 3 forming a second sealing layer on the exposed surface of the first inorganic insulating layer, and cutting a region where the plurality of opening portions are provided. The Rejections The Examiner maintains, and Appellants request review of, the following rejections under 35 U.S.C. § 103(a): 1) Claims 11–14 and 19 as unpatentable over Tamura3 in view of Kida4 and Maruyama5; and 2) Claims 15–18 and 20 as unpatentable over Tamura in view of Kida, Maruyama, and Murade.6 The Issue Presented The dispositive issue presented by Appellants’ arguments is whether the Examiner erred in concluding it would have been obvious for one of ordinary skill in the art to have formed a plurality of opening portions in parts of Tamura’s second inorganic insulating layer exposed by the second opening portion prior to forming a third inorganic insulating layer over the plurality of opening portions and the organic insulating layer. We answer this question in the affirmative and, therefore, will not sustain the Examiner’s rejections based on the proposed combination of Tamura, Kida, and Maruyama, with or without Murade. 3 Tamura et al., US 2007/0196999 A1, patented Aug. 23, 2007. 4 Kida et al., US 2009/0227088 A1, patented Sept. 10, 2009. 5 Maruyama et al., US 2007/0232005 A1, patented Oct. 4, 2007. 6 Murade et al., US 6,897,932 B2, patented May 24, 2005. Appeal 2012-004057 Application 12/423,563 4 ANALYSIS The Examiner finds, and Appellants do not dispute, that Tamura discloses a method of manufacturing a semiconductor device as recited in claim 11 except for the formation of a second inorganic insulating layer on the exposed first opening portion and forming a plurality of opening portions in parts of the second insulating layer exposed by the second opening portion. Ans. 5–6. For the step of forming the plurality of opening portions, the Examiner finds Kida, in Figure 10B, reproduced below, teaches “forming a plurality of opening portions in parts of an inorganic insulating layer, which are exposed by the opening portion.” Id. at 6. Kida, Figure 10B, a partial cross-section depicting grooves 6 formed in the region between plural semiconductor chips on a wafer The Examiner concludes it would have been obvious to incorporate a plurality of opening portions in parts of Tamura’s insulating layer as a scribe line to reduce chipping and damage from dicing as taught by Kida. Appellants contend the combination is based on improper hindsight because Kida’s grooves 6 are formed after formation of the semiconductor wafer, i.e., after forming the stacked layers, whereas Tamura forms the second insulating layer during the process of stacking layers. Appeal Br. 13. Moreover, Appellants note claim 11 requires forming the plurality of Appeal 2012-004057 Application 12/423,563 5 opening portions during the process of stacking layers and forming the semiconductor device. Id. at 12. In response, the Examiner finds Tamura’s third inorganic layer acts as a moisture barrier for the organic insulating layer. Ans. 12, referring to Tamura ¶ [0161]. The Examiner further finds that because groove formation would reduce the effectiveness of the inorganic layer’s moisture barrier function, the step of forming the grooves would preferably be done prior to forming the inorganic layer. Id. Moreover, the Examiner finds performing the step of forming the grooves prior to formation of additional insulating layers “would reduce particle contamination and chipping of the interlayer insulating film that would cause damage to the semiconductor chip.” Id. The Examiner provides no support, nor do we find any, for the Examiner’s findings that the step of forming the grooves, if done after formation of the inorganic insulating layer as taught by Kida, would reduce the effectiveness of the Tamura’s inorganic layer, as well as reduce particle contamination and chipping of the interlayer insulating film. To the contrary, Kida teaches the interlayer insulating film is scribed prior to dicing to avoid chipping in the film from reaching an interlayer insulating layer in a semiconductor chip area. See Kida ¶¶ [0009]–[0010]. Thus, as Appellants contend, the only suggestion in this record for performing the step of forming a plurality of opening portions in a part of a second inorganic insulating layer exposed by a second opening portion prior to forming the third inorganic insulating layer can be found in Appellants’ own disclosure. The fact finder must be aware “of the distortion caused by hindsight bias and must be cautious of arguments reliant upon ex post reasoning.” KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398, 421 (2007) (citing Graham v. Appeal 2012-004057 Application 12/423,563 6 John Deere Co., 383 U.S. 1, 36 (1966) (warning against a “temptation to read into the prior art the teachings of the invention in issue”)). As such, the Examiner has not carried the burden of establishing, by a preponderance of the evidence, the factual basis for the conclusion that the claimed invention would have been obvious. In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) (“It is impermissible to use the claimed invention as an instruction manual or ‘template’ to piece together the teachings of the prior art so that the claimed invention is rendered obvious.”); In re Gorman, 933 F.2d 982, 987 (Fed. Cir. 1991) (“It is impermissible, however, simply to engage in a hindsight reconstruction of the claimed invention, using the applicant's structure as a template and selecting elements from references to fill the gaps.”). Absent such a suggestion in the prior art, the Examiner’s conclusion lacks sufficient rational underpinning. In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (“[R]ejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.”), quoted with approval in KSR, 550 U.S. at 418. We note the Examiner does not rely on Murade to remedy the deficiency in the combination of Tamara, Kida, and Maruyama set forth above. Appeal 2012-004057 Application 12/423,563 7 ORDER Upon consideration of the record, and for the reasons given above and in the Appellants’ Appeal and Reply Briefs, it is ORDERED that the decision of the Examiner rejecting claims 11–20 under 35 U.S.C. § 103(a) is reversed. REVERSED cdc