Ex Parte NUGTEREN et al

Patent Trials and Appeals Board

Mar 27, 2019

14557881 - (D) (P.T.A.B. Mar. 27, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/557,881 12/02/2014
73459 7590 03/29/2019
NIXON & V ANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11 TH FLOOR
ARLINGTON, VA 22203
FIRST NAMED INVENTOR
Cedric NUGTEREN
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SCS-550-1805 6908
EXAMINER
WEI,ZHENG
ART UNIT PAPER NUMBER
2192
NOTIFICATION DATE DELIVERY MODE
03/29/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CEDRIC NUGTEREN and ANTON LOKHMOTOV1
Appeal2018-007302
Application 14/557,881
Technology Center 2100
Before CAROLYN D. THOMAS, JOSEPH P. LENTIVECH, and
SCOTT RAEVSKY, Administrative Patent Judges.
RAEVSKY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Rejection of claims 1 and 3-20, all the pending claims in
the present application (see Claims Appendix). We have jurisdiction over
the appeal under 35 U.S.C. § 6(b).
We AFFIRM.
1 Appellants name Arm Limited as the real party in interest (App. Br. 3).
Appeal2018-007302
Application 14/557,881
STATEMENT OF THE CASE
Appellants' invention generally relates to "an apparatus for
performing data processing in a single program multiple data fashion on a
target data set." See Abstract. Claim 1, reproduced below, is illustrative of
the claimed subject matter:
1. Apparatus for performing data processing in a single
program multiple data fashion on a target data set, the apparatus
compnsmg:
at least one processor configured to execute multiple
threads to perform the data processing; and
a digital data storage configured to store information
defining a plurality of thread schedule configurations, each
thread schedule configuration defining an order in which the
multiple threads are to be executed by the at least one processor,
wherein a first thread schedule configuration and a second thread
schedule configuration of the plurality of thread schedule
configurations each comprise a respectively different order in
which the multiple threads are to be executed,
wherein the at least one processor is further configured to
execute the multiple threads in a selected order defined by a
selected thread schedule configuration of the plurality of thread
schedule configurations in response to a thread schedule
selection signal, and
wherein the at least one processor is further configured to
gather performance data relating to the performed data
processing and to generate the thread schedule selection signal in
dependence on the performance data.
App. Br. 18 (Claims Appendix).
Appellants appeal the following rejection:
Claims 1 and 3-20 are rejected under 35 U.S.C. § 103 as being
unpatentable over Khatri et al. (US 2009/0307698 Al, pub. Dec. 10, 2009),
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Application 14/557,881
Lippett (US 2014/0026141 Al, pub. Jan. 23, 2014), Lindholm et al. (US
9,189,242 B2, iss. Nov. 17, 2015), and Aglietti et al. (US 6,578,065 Bl, iss.
June 10, 2003). Final Act. 7.
We review the appealed rejection for error based upon the issues
identified by Appellants and in light of the arguments and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 107 5 (BP AI 2010)
(precedential).
ANALYSIS
Appellants contend that Khatri and Lippett do not teach or suggest
claim 1 's "digital data storage configured to store information defining a
plurality of thread schedule configurations, each thread schedule
configuration defining an order in which the multiple threads are to be
executed by the at least one processor." App. Br. 8-13; Reply Br. 3-9.
Appellants first contend "the 'thread scheduling' to which Khatri refers is an
ordering of cores in which the cores execute some unknown list of threads,"
and thus, Khatri "does not define an order in which the multiple threads are
to be executed." App. Br. 10. Appellants then contend "Lippett also fails to
rectify Khatri' s deficiencies with respect to disclosing storing plural thread
schedule configurations which each define the order in which the multiple
threads are to be executed." Id. at 12. In particular, Appellants argue,
"Lippett ... describes storing policies and algorithms. An algorithm or
policy, however, is not the same as the data on which an algorithm
operates." Id. at 13.
We find Appellants' arguments unpersuasive. The Examiner finds,
and we agree, that "Khatri combined with the assignment/scheduling thread
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Application 14/557,881
method in [the] Lippett reference define the order of the multiple threads
execution." Final Act. 3. Specifically, Lippett discloses a "two-tier [thread]
scheduling hierarchy," including "a FIFO scheduling algorithm" and a
"scheduler algorithm ... configured as a round robin." Lippett ,r 216. In
other words, Lippett teaches or suggests multiple thread schedule
configurations that each define the order in which multiple threads are to be
executed, including a first-in, first-out (FIFO) thread schedule configuration
and a round robin thread schedule configuration. As such, we are not
persuaded the Examiner erred in finding the combination of Khatri and
Lippet teaches or suggests the disputed limitation.
For the first time on Reply, Appellants argue "it is not clear how
[Lippett] can be combined with Khatri, which instead relies on the ordering
of cores being provided. Reconciling the two different criteria for defining
the order of execution, even if arguendo considered possible, would not be
obvious to a person of skill in the art." Reply Br. 8-9. Appellants have not
explained why this argument, which Appellants could have raised in the
Appeal Brief, was not raised therein. We therefore do not consider this new
argument. See 37 C.F.R. § 4I.41(b)(2); see also In re Hyatt, 211 F.3d 1367,
1373 (Fed. Cir. 2000) (noting that an argument not first raised in the Brief to
the Board is waived on appeal); Ex parte Nakashima, 93 USPQ2d 1834
(BP AI 2010) ( explaining that arguments and evidence not timely presented
in the principal Brief will not be considered when filed in a Reply Brief,
absent a showing of good cause explaining why the argument could not have
been presented in the Principal Brief).
Appellants also contend that the Examiner erred by relying on Aglietti
for the limitation, "at least one processor further configured to gather
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Application 14/557,881
performance data relating to the data processing performed by the execution
circuitry and to generate the thread schedule selection signal in dependence
on the performance data," also recited in claim 1. App. Br. 13-16; Reply
Br. 9-10. Appellants argue combining Aglietti with Khatri would not have
been obvious "because Khatri provides an ordering of cores whereas Aglietti
provides a measurement of efficiency on a specific processor." App. Br. 14.
However, the Appellants overlook-and thus do not dispute-that the
Examiner initially provided a motivation to combine Aglietti with Lindholm.
See Final Act. 10. Specifically, the Examiner finds, and we agree, that "it
would have been obvious ... to incorporate Aglietti' s performance data into
Lindholm's weight data calculation to further schedule/generate schedule
selection signal based on the performance data/figure of merit." Id. The
Examiner's Answer also finds, and we agree, that "it would have been
obvious ... to incorporate Aglietti's performance data into Khatri and [the]
other cited reference [ s] to further schedule/ generate schedule selection
signal based on the performance data/figure of merit in the order the threads
that are executed based on the cores of different CPUs or processors."
Ans. 7.
Accordingly, we sustain the Examiner's rejection of claim 1.
Appellants' arguments regarding the rejection of independent claims 19 and
20 rely on the same arguments presented for independent claim 1, and
Appellants do not argue separate patentability for the dependent claims. See
App. Br. 15-16. We therefore also sustain the Examiner's rejection of
claims 3-20. See 37 C.F.R. § 4I.37(c)(l)(iv).
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Application 14/557,881
DECISION
We affirm the Examiner's 35 U.S.C. § 103 rejection of claims 1 and
3-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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