Ex Parte Moyer et al

Patent Trial and Appeal BoardMar 31, 2014

11748350 (P.T.A.B. Mar. 31, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte WILLIAM C. MOYER and MICHAEL D. SNYDER ____________ Appeal 2011-011748 Application 11/748,350 Technology Center 2100 ____________ Before ELENI MANTIS MERCADER, JASON V. MORGAN, and STANLEY M. WEINBERG, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-011748 Application 11/748,350 2 This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection of claims 1, 3, 4, 6-12, 18, and 20-24. We have reviewed the Examiner’s rejections in light of Appellants’ arguments that the Examiner has erred. We concur with Appellants’ contention that the Examiner erred in finding the combination of James (US 7,117,300 B1, Oct. 3, 2006), Barry (US 2001/0032305 A1, Oct. 18, 2001), and Seeley (US 2004/0205420 A1, Oct. 14, 2004) teaches the limitation of “even when a dirty bit associated with the cache entry indicates that data stored in the cache entry is dirty, the data stored in the cache entry is provided to the debug circuit via the bus and neither the cache entry is modified nor the dirty bit is cleared,” as recited in independent claim 1. As identified by Appellants (App. Br. 10-11; Reply Br. 4-6), James discloses a “content addressable memory” (CAM) for use in a search engine, but does not disclose that the CAM can be used as a cache, a debugging circuit, or not clearing the dirty bit. Barry does not cure the above cited deficiency. Neither Barry nor James teaches data stored in a cache entry provided to the debug circuit and neither Barry nor James discloses the use of a dirty bit. The Examiner relied upon Seeley for a teaching of a dirty bit (¶ [0123]), however the Examiner has not identified where Seeley teaches a cache entry to a debug circuit even when the corresponding dirty bit is dirty, or not modifying or clearing the dirty bit when the data stored in the cache entry is provided to the debug circuit. Therefore, on this record we are constrained to conclude that James, Barry, and Seeley, either alone or in combination, do not teach or suggest the disputed limitation of claim 1. Appeal 2011-011748 Application 11/748,350 3 Accordingly, we will not sustain the Examiner’s rejection of independent claim 1 and for the same reasons the rejections of claims 3, 4, 6-12, 18, and 20-24, which have similar limitations (App. Br. 12). DECISION The decision of the Examiner to reject claims 1, 3, 4, 6-12, 18, and 20-24 is reversed. REVERSED msc