Ex Parte Motwani et al

Patent Trial and Appeal Board

Dec 21, 2016

13780690 (P.T.A.B. Dec. 21, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/780,690 02/28/2013 Ravi H. Motwani 110578-189399 (P53204) 1361
31817 7590 12/23/2016
SCHWABE, WILLIAMSON & WYATT, P.C.
c/o CPA GLOBAL
900 2nd Avenue South, Suite 600
MINNEAPOLIS, MN 55402
EXAMINER
CHAUDRY, MUJTABA M
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
12/23/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAVI H. MOTWANI and KIRAN PANGAL
Appeal 2016-004553
Application 13/780,690
Technology Center 2100
Before BRADLEY W. BAUMEISTER, JON M. JURGOVAN, and
JOSEPH P. LENTIVECH, Administrative Patent Judges.
BAUMEISTER, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1—20. App. Br. 2.1 We affirm-in-part.
1 Rather than repeat the Examiner’s positions and Appellants’ arguments in
their entirety, we refer to the following documents for their respective
details: the Final Action mailed February 20, 2015 (“Final Act.”); the
Appeal Brief filed October 7, 2015 (“App. Br.”); the Examiner’s Answer
mailed January 22, 2016 (“Ans.”); and the Reply Brief filed March 21, 2016
(“Reply Br.”).
Appeal 2016-004553
Application 13/780,690
STATEMENT OF CASE
Appellants describe the present invention as follows:
Embodiments include device, storage media, and methods
for decoding a codeword of encoded data. In embodiments, a
processor may be coupled with a decoder and configured to
multiply the codeword and a parity-check matrix of the encoded
data to produce a syndrome. If the syndrome is non-zero then
the processor may identify a bit error in the codeword based at
least in part on a comparison of the syndrome to one or more
columns of the parity-check matrix.
Abstract.
Appellants further explain that “[i]n some embodiments, the controller
may be configured to perform a multi-bit error correction if the single-bit
error correction fails.” Spec. 111.
Independent claim 1, reproduced below, is illustrative of the appealed
claims:
1. An apparatus comprising:
a memory to store a codeword of an encoded data; and
a controller coupled with the memory to:
compute a syndrome of the encoded data when
reading the encoded data from the memory;
determine whether the encoded data contains at
least one bit of error based at least in part on the syndrome;
first attempt to correct the at least one bit of error
with a single-bit correction process; and
second attempt to correct the at least one bit of error
with a multi-bit correction process if the first attempt fails
to correct the entire at least one bit of error due to the
encoded data having multi-bit errors;
wherein compute a syndrome includes multiply a
multi-column parity-check matrix and the codeword of the
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Application 13/780,690
encoded data read from the memory to produce the
syndrome of the encoded data;
wherein determine includes determine whether the
syndrome is non-zero; and
wherein the first attempt includes identify a single
bit error in the codeword of the encoded data based at least
in part on a comparison of the non-zero syndrome to one
or more columns of the parity-check matrix.
Claims 1—20 stand rejected under 35 U.S.C. § 103(a) as obvious over
Fujiwara (US 2009/0106633 Al; published Apr. 23, 2009) in view of
Ou (US 2006/0031741 Al; published Feb. 9, 2006).
We have jurisdiction under 35 U.S.C. § 6(b). We review the appealed
rejections for error based upon the issues identified by Appellants, and in
light of the arguments and evidence produced thereon. Ex parte Frye,
94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).
FINDINGS AND CONTENTIONS
The Examiner finds that Fujiwara computes a syndrome of the
encoded data when reading the encoded data from the memory; determines
whether the encoded data contains at least one bit of error based at least in
part on the syndrome; and first attempts to correct the at least one bit of error
with a single-bit correction process. Ans. 3. The Examiner further finds that
Fujiwara teaches (1) that the computing of a syndrome includes multiplying
a multiple-column parity-check matrix and the codeword of the encoded
data read from the memory to produce the syndrome of the encoded data;
and (2) that the error determination includes determining whether the
syndrome is non-zero. Id.
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Application 13/780,690
The Examiner finds that “Fujiwara does not explicitly teach a second
attempt to correct the at least one bit of error with a multi-bit correction
process if the first attempt fails to correct the entire at least one bit of error
due to the encoded data having multi-bit errors.’ '' Id. at 4. The Examiner
reasons, though, that “if the error is not detected/corrected based on the
single-bit error correction process[,] then it is obviously possible and
inherently true that the number of errors are greater than a single bit.” Id.
The Examiner concludes that it would have been an obvious engineering
design choice to subsequently attempt a multi-bit error correction process if
the initial single-bit error correction process fails because “using the multi­
bit error detection/correction process of Fujiwara would have been the next
logical choice to detect and correct the errors in the received data.” Id.
The Examiner Further finds that “Fujiwara does not explicitly teach
[identifying] a single bit error in the codeword of the encoded data based at
least in part on a comparison of the syndrome to one or more columns of the
parity-check matrix[,] as stated in the present application.” Id. at 5. The
Examiner further finds, though, that Ou teaches this missing limitation. Id.
at 5—6. And the Examiner concludes that it would have been obvious to
combine the references’ teachings. Id. at 6.
Appellants assert that
Fujiwara teaches to make a single attempt to correct one or more
errors in a byte using a process for detecting and correcting
multiple bit errors. Fujiwara, even in combination with Ou,
provides no teaching or suggestion to cause one skilled in the art
to “first attempt to correct the at least one bit of error with a
single-bit correction process; and second attempt to correct the
at least one bit of error with a multiple-bit correction process if
the first attempt fails to correct the entire at least one bit of error
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Application 13/780,690
due to the encoded data having multi-bit errors,” as recited in
claim 1.
Reply Br. 3.
Appellants do not present separate, substantive arguments with
respect to any of the other pending claims. App. Br. 8—9; Reply Br. 3^4.
ANALYSIS
/.
The Examiner does not provide sufficient evidence either that (1) the
cited prior art’s error correction process inherently first performs a complete
single-bit error correction process and then subsequently performs a multi­
bit correction process; or that (2) it at least would have been on obvious
engineering design choice to detect and correct error bits in a one-by-one-bit
sequential manner. Instead, the passages cited by the Examiner and
Appellants (see Ans. 3—5, 16—20; App. Br. 5—6; Reply Br. 2—3) appear to
indicate that Fujiwara describes a single process for correcting multiple
spotty-byte errors within a byte. App. Br. 6 (citing Fujiwara 139). This
process appears to detect and attempt to correct all of the plural errors in a
single parallel process—not in separate, serially performed processes:
As explained below, when [plural] errors occurred in the
transmitted word (V) 31 (namely, when the received word 32
includes the errors), the [singular] correcting and detecting
process for the [plural] errors can be executed based on the
[single] value of a syndrome (S) 33 generated by using the
(90,64) [4i/8EC]2 code shown in FIG. 3.
Fujiwara 1237 (summarizing section of the Specification’s disclosure:
“The Decoding Method and the Configuration of the Circuit for Realizing
the Decoding Method”). See also Fujiwara ^fl[ 238-42 (further explaining
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Application 13/780,690
how a single syndrome S is used to express the occurrence of multiple
errors).
For the foregoing reasons, Appellants have persuaded us of error in
the Examiner’s obviousness rejection of independent claim 1. Accordingly,
we do not sustain the Examiner’s rejection of that claim or of independent
claim 10, which is directed to a non-transitory computer readable media
comprising instructions to cause an apparatus to make serial attempts to
correct at least one bit of error, first with a single-bit correction process, and
subsequently with a multi-bit process. We likewise do not sustain the
obviousness rejection of claims 2—9 and 11—13, which depend from these
independent claims.
II.
Independent claim 14 is reproduced below with emphasis added:
14. A method of identifying a bit error comprising:
reading, by a controller, a codeword of an encoded data
stored in a non-volatile memory;
computing, by the controller, a syndrome of the encoded
data using the codeword;
determining, by the controller, whether the encoded data
contains at least one bit of error based at least in part on the
syndrome;
first attempting, by the controller, to correct the at least
one bit of error with a single-bit correction process; and
second attempting, by the controller, to correct the at least
one bit of error with a multibit correction process if the first
attempt fails to correct the entire at least one bit of error due to
the encoded data having multi-bit errors',
wherein computing a syndrome includes multiplying, by
the controller, a multi-column parity-check matrix and the
codeword to identity the syndrome of the encoded data;
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Application 13/780,690
wherein determining includes determining whether the
syndrome is non-zero; and
wherein first attempting includes identifying, by the
controller, a single bit error based at least in part on matching the
non-zero syndrome to one or more columns in the plurality of
columns of the parity-check matrix.
Unlike claims 1 and 10, which are directed to an apparatus and a
computer readable media, respectively, claim 14 is directed to a method of
identifying a bit error. This fact is significant because claim 14 includes a
conditional method step. Specifically, the step of “second attempting ... to
correct the at least one bit of error with a multibit correction process” is
conditioned upon the first attempt failing to correct the entire error.
Restated, the second attempting step only need be performed in those
circumstances in which the first attempting step fails to correct the error.
That is, claim 14 reads on a method that includes performing only a single­
bit correction process, without performing a multi-bit correction process—at
least in those situations where the single-bit correction process is successful.
See Ex parte Schulhauser, at 10 (PTAB 2016) (precedential) (confirming
that “‘[i]f the condition for performing a contingent step is not satisfied, the
performance recited by the step need not be carried out in order for the
claimed method to be performed’” (citation omitted)).
Furthermore, the only deficiency in the obviousness rejection that
Appellants argued on appeal is that Fujiwara fails to disclose performing the
second, multi-bit correction process. See generally App. Br.; Reply Br. As
such, Appellants have not established that the Examiner erred in rejecting
method claim 14, or dependent claims 15—20, as obvious over the
combination of Fujiwara and Ou. See Frye, 94 USPQ2d at 1075 (holding
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Application 13/780,690
that the Board reviews the appealed rejections for error based upon the
issues identified by Appellants, and in light of the arguments and evidence
produced thereon).
DECISION
The Examiner’s decision rejecting claims 14—20 is affirmed.
The Examiner’s decision rejecting claims 1—13 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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