Ex Parte Morris

Patent Trial and Appeal Board

Oct 24, 2012

10245106 (P.T.A.B. Oct. 24, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte DALE MORRIS
_____________

Appeal 2010-004058
Application 10/245,106
Technology Center 2100
______________

Before HOWARD B. BLANKENSHIP, JUSTIN T. ARBES, and
BRYAN F. MOORE, Administrative Patent Judges.

MOORE, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-004058
Application 10/245,106

2
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 16-23. App. Br. 2. Claims 1-15 were canceled. App.
Br. 6. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE the Examiner’s rejection of these claims and enter a
new ground of rejection.

INVENTION
The invention is directed to indirectly indexing general-purpose
registers. See Spec. [06].

Claims 16 is representative of the invention and reproduced
below:
16. A microprocessor comprising:
registers, each of said registers having plural locations at
different positions within that register;
an instruction decoder for decoding instructions, said
instructions including first and second indirect-indexing
instructions, said first indirect-indexing instruction specifying a
first index register of said registers, a first result register of said
registers, and a first position of said positions, said second
indirect-indexing instruction specifying a second index register
of said registers, a second result register of said registers, and a
second position of said positions, said second position being
different from said first position; and
an execution unit for executing
said first indirect-indexing instruction so as to write a
first result at said first position within said first result register,
said first result being at least in part a function of data stored at
a first data-storage location at a third position within a first
data-storage register of said registers, said first data-storage
register and said third position being determined by a first index
stored at said first position within said first index register, and
Appeal 2010-004058
Application 10/245,106

3
said second indirect-indexing instruction so as to write a
second result at said second position within said second result
register, said second result being at least in part a function of
data stored at a second data-storage location at a fourth position
within a second data-storage register of said registers, said
second data-storage register and said fourth position being
determined by a second index stored at said second position
within said second index register.

REFERENCES
Corcoran US 5,442,769 Aug. 15, 1995
Agarwal US 5.890,222 Mar. 30, 1999

REJECTION AT ISSUE
Claims 16-23 were rejected as unpatentable under 35 U.S.C. § 103(a)
as being obvious over the combination of Agarwal and Corcoran. Ans. 3-9.

ISSUES
Did the Examiner incorrectly determine that Agarwal and Corcoran
can be combined under 35 U.S.C. § 103(a)?
1

ANALYSIS
Appellant’s arguments have persuaded us of error in the Examiner’s
rejection of claims 16-23.
Concerning the § 103 rejection of independent claim 16, the Examiner
acknowledges that
Agarwal does not teach that the first and second instructions
indicate a first position of said positions and a second position

1
Appellant makes additional arguments regarding claims 16 and 19. App.
Br. 13-21. Because the above issue is dispositive of the case, however, we
need not reach these additional issues.
Appeal 2010-004058
Application 10/245,106

4
of said positions, said second position being different from said
first position, or that the result of the first and second
instructions are written to the first and second position within
the first and second result registers, the first and second results
being at least in part a function of data stored at a data storage
location at third and fourth positions within first and second
data storage registers, or wherein the third and fourth positions
are determined by the first and second indexes stored at the first
and second positions within the index register [,]
but finds that Corcoran discloses these limitations of the claim. Ans. 6-8.
The Examiner concludes that it would have been obvious for one with
ordinary skill in the art to have used the register and portion specifiers,
specifying portions of registers, as taught by Corcoran, in the indirect
register addressing index register address fields taught by Agarwal to meet
the above limitations. Id. at 8. The Examiner finds that one of ordinary skill
in the art at the time of the invention would have been motivated to make
this combination “[to provide a processor with efficient processing of
different-sized data, which can vary depending on the external source
(e.g., a host processor), which also decreases the amount of wasted
register space (column 2, lines 6-42)], and combining the portion specifiers
would server [sic] to further decrease wasted space.” Id. at 8.
We agree with Appellant that a person of ordinary skill in the art
would not have had reason to combine the teachings of Agarwal and
Corcoran in the manner proposed by the Examiner. See App. Br. 14-15;
Reply Br. 2-6. It is undisputed that Corcoran teaches portion specifiers (col.
2, l. 45-col. 3, l. 3). However, the record before us contains no articulated
reasoning with some rational underpinning as to why one with ordinary skill
in the art would have placed the portion specifiers of Corcoran in the indirect
register addressing index register address fields of Agarwal. The portion
Appeal 2010-004058
Application 10/245,106

5
specifiers of Corcoran are applicable to co-processors which must deal with
host processors that may have different data sizes; thus, the co-processor of
Corcoran must “be able to easily process data of different sizes.” App. Br.
14; Reply Br. 3 (citing Corcoran, col. 2, ll. 7-11). Because of this
requirement, there may be wasted register space; for example, a 32 bit
register may be used to store a single byte. Reply Br. 3 (citing Corcoran,
col. 2, ll. 25-29). Corcoran’s teachings would have no applicability to
processors that do not waste register space due to a mismatch between
register size and data size. Reply Br. 4. In contrast, Agarwal’s processing
elements do not participate in host processor to co-processor
communications that would implicate the Corcoran wasted space problem.
See App. Br. 14-15; Reply Br. 5.
The Examiner acknowledges that “Agarwal does not explicitly teach
the need for handling different sized data (such as from the examples given
in Corcoran).” Ans. 10. To deal with this deficiency of Agarwal, the
Examiner finds that “any general purpose processor could be required to
deal with data of different sizes.” Id. (emphasis added). However, the
Examiner does not present any evidence to support this statement or to show
that any general purpose processor would be subject to the wasted space
problem of Corcoran. Moreover, the Examiner’s statement that a general
purpose processor “could” deal with different sized data is insufficient to
explain why a person of ordinary skill in the art would have had reason to
combine the specific processor disclosed in Agarwal with the teachings of
Corcoran, particularly given the differences between the references
explained above.
Appeal 2010-004058
Application 10/245,106

6
The Examiner also finds that:
Agarwal does teach a processing unit that is part of a
SIMD processor (column 2, lines 55-60) . . . [and a] normal
SIMD system comprises a number of processing units and, in
this case (having multiple processing units), any processor of
the group could be considered a “coprocessor” and would have
to deal with external instructions and data which may be of
varying sizes.
Id. Again, the Examiner provides no evidence to support this statement or to
show, for example, that the multiple processors in a SIMD system in fact
deal with data of different sizes or that the SIMD processor disclosed in
Agarwal would ever need to deal with data of different sizes. Finally, the
Examiner states without support that the portion specifiers of Corcoran “are
not taught . . . to provide benefit only in a coprocessor environment . . . [and
o]ne of ordinary skill in the art, at the time the invention was made, would
recognize that all of these advantages provided by the combination would
apply to a processor, and provide a motivation for said combination” Id.
“[R]ejections on obviousness grounds cannot be sustained by mere
conclusory statements; instead, there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (cited with
approval in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417-18 (2007)).
Here, the Examiner has not supplied an articulated reasoning with some
rational underpinning to support the above conclusory statements.
For the reasons stated above, we do not sustain the Examiner’s
35 U.S.C. § 103(a) rejection of independent claim 16, independent claim 20
which contains essentially the same limitations discussed above and whose
rejection likewise is based on the combination of Agarwal and Corcoran,
Appeal 2010-004058
Application 10/245,106

7
and claims 17-19, and 21-23 dependent thereon, as unpatentable over the
combination of Agarwal and Corcoran.
NEW GROUND OF REJECTION
We enter the following new ground of rejection pursuant to our
authority under 37 C.F.R. § 41.50(b).

PRINCIPLES OF LAW
Transitory propagating signals are unpatentable under 35 U.S.C.
§ 101. In re Nuijten, 500 F.3d 1346, 1355 (Fed. Cir. 2007). According to
U.S. Patent & Trademark Office (USPTO) guidelines:
A claim that covers both statutory and non-statutory
embodiments . . . embraces subject matter that is not eligible for
patent protection and therefore is directed to non-statutory
subject matter. . . . For example, a claim to a computer readable
medium that can be a compact disc or a carrier wave covers a
non-statutory embodiment and therefore should be rejected
under § 101 as being directed to non-statutory subject matter.
U.S. Patent & Trademark Office, Interim Examination Instructions for
Evaluating Subject Matter Eligibility Under 35 U.S.C. § 101, Aug. 2009, at
2, available at http://www.uspto.gov/web/offices/pac/dapp/opla/2009-08-
25_interim_101_instructions.pdf (“Interim Instructions”).
The USPTO also provides the following guidance:
The broadest reasonable interpretation of a claim drawn to a
computer readable medium . . . typically covers forms of non-
Appeal 2010-004058
Application 10/245,106

8
transitory tangible media and transitory propagating signals per
se in view of the ordinary and customary meaning of computer
readable media, particularly when the specification is silent. . . .
When the broadest reasonable interpretation of a claim covers a
signal per se, the claim must be rejected under 35 U.S.C. § 101
as covering non-statutory subject matter.
David J. Kappos, Subject Matter Eligibility of Computer Readable Media,
1351 Off. Gaz. Pat. Office 212 (Feb. 23, 2010).

ANALYSIS
35 U.S.C. § 101 Rejection
Claim 20
Independent claim 20 recites, in pertinent part, “[a] computer-readable
media comprising a program of computer-executable instructions.” Upon
reviewing Appellant’s Specification for context, we do not find any
explanation for what constitutes the claimed “computer-readable media.”
Therefore, because Appellant’s Specification is silent in this regard, we
conclude that the claimed “computer-readable media” can be broadly, but
reasonably, construed to encompass both non-transitory tangible media and
transitory propagating signals per se. As independent claim 20 covers both
statutory and non-statutory embodiments, it embraces subject matter that is
not eligible for patent protection and, therefore, is directed to non-statutory
subject matter. We enter a new ground of rejection of claim 20 under 35
U.S.C. § 101 as being directed to non-statutory subject matter.
Appeal 2010-004058
Application 10/245,106

9
Claims 21-23
For the same reason set forth above, dependent claims 21-23 are also
directed to non-statutory subject matter under 35 U.S.C. § 101.

DECISION
The Examiner’s decision to reject claims 16-23 is reversed. We
newly reject claims 20-23 as being directed to non-statutory subject matter
under 35 U.S.C. § 101. 37 C.F.R. § 41.50(b) provides that “[a] new ground
of rejection pursuant to this paragraph shall not be considered final for
judicial review.” 37 C.F.R. § 41.50(b) also provides that Appellants,
WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must
exercise one of the following two options with respect to the new grounds of
rejection to avoid termination of proceedings (37 C.F.R. § 1.197 (b)) as to
the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of the
claims so rejected or new evidence relating to the claims so rejected,
or both, and have the matter reconsidered by the examiner, in which
event the proceeding will be remanded to the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard under
37 C.F.R. § 41.52 by the Board upon the same record. . . .

No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

REVERSED; 37 C.F.R. § 41.50(b)
ELD