Ex Parte Meyer

Patent Trial and Appeal Board

Mar 30, 2016

12326515 (P.T.A.B. Mar. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/326,515 12/02/2008
25281 7590 04/01/2016
DICKE, BILLIG & CZAJA
FIFTH STREET TOWERS
100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS, MN 55402
FIRST NAMED INVENTOR
Thorsten Meyer
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
I560.246.101/2008P51664US 3527
EXAMINER
CRAWFORD, LATANYAN
ART UNIT PAPER NUMBER
2813
NOTIFICATION DATE DELIVERY MODE
04/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
USPTO.PA TENTS@dbclaw.com
dmorris@dbclaw.com
DBCLA W-Docket@dbclaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte THORSTEM MEYER
Appeal2014-004483
Application 12/326,515
Technology Center 2800
Before KAREN M. HASTINGS, MICHAEL P. COLAIANNI, and
WESLEY B. DERRICK, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 the final rejection of claims
1-3, 5-7, 23, and 25. Claims 8-22 are withdrawn from consideration as
being drawn to a non-elected invention. Claims 4 and 24 are cancelled.
(Claims App'x). We have jurisdiction over the appeal pursuant to 35 U.S.C.
§ 6(b ).
We AFFIRM.
Appellant's invention is directed to semiconductor package 20 that
includes one or more electrically insulating elements 24 each having one or
more through-holes 30, the through-holes are filled with electrically
Appeal2014-004483
Application 12/326,515
conducting material 28 to provide embedded semiconductor package 20 with
a wide range of flexibility for Z-directional interconnectivity to
semiconductor chips 22 in the package and to components stacked on the
package (Spec. 3:14-19; Claim 1).
Claim 1 is illustrative:
1. A semiconductor device comprising:
a semiconductor chip including an active first face including a
plurality of contacts and an opposing inactive second face;
one or more electrically insulating elements separated from the
semiconductor chip by a space, each electrically insulating element defining
a plurality of through-holes;
encapsulation material disposed in the space and around the
semiconductor chip and around the electrically insulating elements, wherein
the encapsulation material together with the semiconductor chip and the one
or more electrically insulating elements form an encapsulation body having
a first main surface proximate to and in parallel with the active first face and
an opposing second main surface proximate to and in parallel with the
inactive second face;
electrically conducting material deposited in the plurality of through-
holes of the one or more electrically insulating elements and extending
between the first and second main surfaces but not beyond the through-
holes;
a first redistribution layer disposed on the first main surface
comprising a plurality of electrically conductive traces electrically
connecting at least a portion of the contacts on the active first face of the
semiconductor chip to the electrically conducting material in up to all
of the plurality of through-holes; and
a second redistribution layer disposed on the second main surface
comprising a plurality of landing pads arranged across the second main
surface at positions within an area defined by a perimeter of the
semiconductor chip and in areas beyond the area defined by the
perimeter of the semiconductor chip, and including a plurality of electrically
conductive traces electrically connecting at least a portion of the landing
pads to the electrically conducting material in up to all of the plurality of the
through-holes so that the portion of landing pads are in electrical
communication with the first redistribution layer via the second
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Appeal2014-004483
Application 12/326,515
redistribution layer and the electrically conducting material in the through-
holes.
Appellant appeals the following rejections 1:
1. Claims 1-32, 6, and 7 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Goller (US 2006/0087044 Al published April 27,
2006) in view of Taniguchi (US 2005/0009243 Al published January
13, 2005).
2. Claims 5, 23, and 25 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Goller in view of Taniguchi and Oh (US
2009/0200652 Al published August 13, 2009).
Regarding rejections (1) and (2), Appellant's arguments focus on the
subject matter common to independent claims 1 and 23 (App. Br. 6-10). We
select claim 1 as representative. Accordingly, claims 2-7, 23 and 25 will
stand or fall with our analysis regarding the rejection of claim 1.
FINDINGS OF FACT AND ANALYSES
1 The Examiner cites to Tsukamoto US 2004/0178492 Al published
September 16, 2004. We shall not consider the Tsukamoto reference in our
analysis of the rejection because there is no excuse for the Examiner not
positively including the reference in the statement of the rejection. In re
Hoch, 428 F.2d 1341, 1342 n.3 (CCPA 1970).
2 Claim 3 was inadvertently omitted from the statement of the 35 U.S.C. §
103 rejection in the Final Office Action (Final Act. 4). However, we
consider this omission harmless error as the Examiner includes claim 3 in
the statement of rejection in the Answer (Ans. 8) and Appellants' arguments
in the Reply Brief indicate that Appellants understand that claim 3 is under
this § 103 rejection (Reply Br. 5).
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Appeal2014-004483
Application 12/326,515
The Examiner's findings and conclusions regarding the teachings of
Goller and Taniguchi are located on pages 4-6 of the Final Action. The
Examiner finds that Goller teaches the subject matter of claim 1, except for
one or more electrically insulating elements separated from the
semiconductor chip by a space, each electrically insulating element defining
at least one of a plurality of through-holes, the encapsulating of the chip and
electrically insulating material, and electrically conducting material
deposited in the plurality of through-holes as recited in claim 1 (Final Act. 4-
5). The Examiner finds that Taniguchi discloses a semiconductor device
that include one or more electrically insulating elements 42 having through-
holes formed there through and spaced from the semiconductor chip 20 with
electrically conductive material deposited in the through-holes (Final Act. 5-
6). The Examiner finds that Taniguchi teaches encapsulating the spaced,
electrically insulating elements along with the semiconductor chip with
material 60. Id. The Examiner concludes that it would have been obvious to
modify the invention of Goller with Taniguchi' s teachings in order to
provide a semiconductor device of high electrical reliability (Final Act. 6).
Appellant argues that Taniguchi's conventional technique for forming
electrical vias teaches away from combining with Goller which teaches that
conventional via forming techniques are unsatisfactory and incapable of
forming highly miniaturized electrical vias as taught by Goller (App. Br. 8).
Appellant contends that Goller discloses using a patterned photoresist to
form miniature columnar vias such that using Taniguchi' s insulating sections
42 with conductive sections 50 would destroy Goller's goal of miniaturizing
system carriers (App. Br. 8).
A reference may be said to teach away when a person of ordinary
skill, upon reading the reference, would be discouraged from
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Appeal2014-004483
Application 12/326,515
following the path set out in the reference, or would be led in a
direction divergent from the path that was taken by the applicant. The
degree of teaching away will of course depend on the particular facts;
in general, a reference will teach away if it suggests that the line of
development flowing from the reference's disclosure is unlikely to be
productive of the result sought by the applicant. ... Although a
reference that teaches away is a significant factor to be considered in
determining unobviousness, the nature of the teaching is highly
relevant, and must be weighed in substance.
In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994).
Contrary to Appellant's argument, Goller discloses:
Both when coating with subsequent laser removal and when
coating an auxiliary carrier by printing, it is not possible to achieve
the precision and fineness which are possible with photosensitive
layers. To achieve a high degree of miniaturization, use is therefore
preferably made of a photosensitive layer and subsequent patterning
using mask techniques in order to coat the auxiliary carrier. (emphasis
added) (iT 5).
The nature of Goller's teaching is merely a preference for using
photosensitive layers to form the vias. Goller teaches that laser removal and
printing are two techniques that do not achieve the desired degree of
miniaturization. These teachings do not disparage or indicate that all
conventional techniques of forming vias would have been unlikely to
produce the result sought by Appellant. We do not find that Goller teaches
away from using Taniguchi' s via forming method that use bar 40 with
through-holes filled with copper to form the vias in a semiconductor
package.
Appellant argues for the first time in the Reply Brief that the
Examiner's reason for combining Goller and Taniguchi (i.e., to enhance
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Appeal2014-004483
Application 12/326,515
reliability) is faulty (Reply Br.4). Appellant contends that the cross sectional
area at the extremity of the conductive sections 50 (i.e., vias) being greater
than the cross-sectional area of the lengthwise portion of the conductive
sections 50 produces the high electrical reliability (Reply Br. 4).
It is improper for Appellant to raise new arguments in the Reply Brief.
37 CPR 41.41(b)(2). The Examiner has maintained since at least the Final
Action that the combination of Goller and Taniguchi would have been
obvious in order to provide greater reliability to the device. There appears to
be no reason why this argument was not presented in the principal Brief.
Nevertheless, Goller and Taniguchi teach using vias with wider bases
(Goller, Fig. 1, ref. no. 6 and 7; Taniguchi, Fig. 4b, ref. no. 50, 58).
Accordingly, the substitution of vias formed by photoetching with vias
formed according to Taniguchi is nothing more than the predictable use of a
prior art element (i.e., vias) according to its intended function (i.e., providing
electrical connections within the semiconductor package). The combination
would still possess the sought after reliability taught by Taniguchi
On this record, we affirm the Examiner's§ 103 rejections.
DECISION
The Examiner's decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
ORDER
AFFIRMED
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