Ex Parte Master et al

Patent Trial and Appeal BoardNov 9, 2012

09997530 (P.T.A.B. Nov. 9, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 09/997,530 11/30/2001 Paul L. Master 046301-002000 6090 70604 7590 11/13/2012 NIXON PEABODY LLP 401 9TH STREET, N.W. WASHINGTON, DC 20004 EXAMINER VICARY, KEITH E ART UNIT PAPER NUMBER 2183 MAIL DATE DELIVERY MODE 11/13/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte PAUL L. MASTER, STEPHEN J. SMITH, and JOHN WATSON ____________ Appeal 2011-001062 Application 09/997,530 Technology Center 2100 ____________ Before JOSEPH F. RUGGIERO, JOHN A. JEFFERY, and ANDREW CALDWELL, Administrative Patent Judges. JEFFERY, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 182-305. We have jurisdiction under 35 U.S.C. § 6(b), and we heard the appeal on November 6, 2012. We reverse. STATEMENT OF THE CASE Appellants’ invention configures integrated circuitry for adaptive or reconfigurable computing. Specifically, an interconnection network configures and reconfigures computational elements for different functions responsive to configuration information. See generally Abstract. Claim 182 is illustrative: Appeal 2011-001062 Application 09/997,530 2 182. A system for adaptive configuration, the system comprising: a memory adapted to store configuration information including a first configuration information and a second configuration information; a first computational unit having a configurable basic architecture including a first plurality of heterogeneous computational elements and a first interconnection network configurably coupling the first plurality of heterogeneous computational elements together, the first interconnection network configuring interconnections between the first plurality of heterogeneous computational elements in response to the first configuration information to perform a basic computational function; and a second computational unit having a configurable complex processing architecture including a second plurality of heterogeneous computational elements and a second interconnection network configurably coupling the second plurality of heterogeneous computational elements together, the second interconnection network configuring interconnections between the second plurality of heterogeneous computational elements in response to the second configuration information to perform a complex processing function. THE REJECTIONS 1. The Examiner rejected claims 182-246, 248-276, and 278-305 under 35 U.S.C. § 103(a) as unpatentable over Wise (US 5,768,561; June 16, 1998) and Baxter (US 5,794,062; Aug. 11, 1998). Ans. 3-16. 1 2. The Examiner rejected claims 247 and 277 under 35 U.S.C. § 103(a) as unpatentable over Wise, Baxter, and Cohen (US 6,005,943; Dec. 21, 1999). Ans. 16-17. 1 Throughout this opinion, we refer to (1) the Appeal Brief filed March 22, 2010 (“App. Br.”); (2) the Examiner’s Answer mailed June 18, 2010 (“Ans.”); and (3) the Reply Brief filed August 18, 2010 (“Reply Br.”). Appeal 2011-001062 Application 09/997,530 3 THE OBVIOUSNESS REJECTION OVER WISE AND BAXTER The Examiner finds that Wise’s adaptive configuration system in Figure 137 has every recited feature of representative claim 1 including a “first computational unit” with (1) “first plurality of heterogeneous computational elements” including adder, subtractor, and multiplier components before the “common block,” and (2) a “first interconnection network,” namely the first portion of the “common block” which is said to configurably couple components at the Y inputs to perform a “basic computational function,” namely either add or subtract. Ans. 4, 17-20, 22- 25. The Examiner also finds that Wise discloses a “second computational unit” with (1) “second heterogeneous computational elements” including carry-save multipliers and resolving adder/subtractors, and (2) a “second interconnection network,” namely the second portion of the “common block” which is said to configurably couple components at the X outputs to perform a “complex processing function,” namely carry-save or matrix multiplier functions. Id. Although the Examiner acknowledges that Wise lacks memory adapted to store first and second configuration information, the Examiner cites Baxter as teaching this feature in concluding that the claim would have been obvious. Ans. 5-6, 21. Appellants argue that while Wise reconfigures specific functions via instructions from tokens, Wise lacks interconnection networks that configure interconnections between computational elements to configurably couple the elements together as claimed. App. Br. 11-16; Reply Br. 2-8. According to Appellants, Wise’s inverse discrete cosine transformation (IDCT) block in Figure 137 is a single computational unit with one function with fixed circuits that are not reconfigurable. Id. Appeal 2011-001062 Application 09/997,530 4 ISSUE Under § 103, has the Examiner erred in rejecting claim 182 by finding that Wise and Baxter collectively would have taught or suggested first and second computational units with respective interconnection networks that each configure interconnections between their respective heterogeneous computational elements responsive to configuration information to configurably couple the elements together? ANALYSIS We begin by noting that since this dispute turns on the Examiner’s findings regarding Wise, we confine our discussion to that reference. As noted above, the Examiner (Ans. 4, 17-20, 22-25) maps the recited first and second interconnection networks to respective parts of the “common block” of Wise’s IDCT architecture in Figure 137 reproduced below. Appeal 2011-001062 Application 09/997,530 5 Wise’s IDCT architecture in Figure 137 But even assuming that the arithmetic elements (adders, subtractors, and multipliers) on both sides of the “common block” are “heterogeneous computational elements,” 2 we still fail to see how the common block configures interconnections between these respective elements to configurably couple them together as the Examiner asserts. Ans. 4-5, 17-20, 22-25. As shown in Figure 11, Wise’s IDCT block transforms frequency data into spatial data and, as the last block in a spatial decoder, 3 provides input to 2 Although we do not agree with the Examiner’s somewhat puzzling and contradictory statement that “[A]pplicant’s claim language did indicate that the first and second computational units are different and distinct from each other, therefore one computational unit can read on both” (Ans. 22-23 (emphases added)), the Examiner in the rejection nonetheless maps distinct “computational units” in Wise to the recited first and second computational units, albeit sharing the “common block” (but comprising different components within this block). Ans. 4-5. To the extent that the Examiner raises an alternative position in the Response to Arguments section in the Answer, we decline to reach that newer position; rather, we review the Examiner’s final rejection in appeals under 35 U.S.C. § 134(a). See In re Webb, 916 F.2d 1553, 1556 (Fed. Cir. 1990). But even if we were to consider this alternative position, it is incorrect, for when a claim requires two separate elements, one element construed as having two separate functions does not meet the claim’s terms. See Lantech, Inc. v. Keip Mach. Co., 32 F.3d 542, 547 (Fed. Cir. 1994); see also In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) (claims requiring three separate means not anticipated by structure containing only two means using one element twice). 3 Since Wise’s Figure 11 shows IDCT block 83 separate from start code detector (SCD) 51 (i.e., they are the first and last blocks in the spatial decoder of that figure), Appellants’ contention that Wise’s IDCT block in Figure 137 is part of the SCD (App. Br. 12; Reply Br. 3) is inconsistent with Appeal 2011-001062 Application 09/997,530 6 a temporal decoder. Wise, col. 8, l. 16; col. 37, l. 42 – col. 38, l. 13; col. 259, l. 31 – col. 260, l. 8; col. 262, ll. 14-54; Figs. 11, 137. Wise’s Figure 139 shows a block diagram of the IDCT relevant to processing tokens—a key data structure used to distribute control and data information throughout the system. Wise, Abstract; col. 12, ll. 49-52 (defining “token”); col. 26, l. 44 – col. 31, l. 12 (describing tokens); col. 263, l. 33 – col. 264, l. 53; Fig. 139. 4 Notably, all blocks in the IDCT, including the one-dimensional IDCT transform blocks 443, 445, recognize DATA tokens—not control tokens: the control tokens are ignored and pass through unchanged. See Wise, col. 263, ll. 40-44, 60-62; col. 264, ll. 21-24 (block 443), 41-45 (block 445); col. 266, l. 38 – col. 267, l. 48; Figs. 139-141. The IDCT is therefore not controlled by control tokens, but rather by various control signals (“latch,” “sel_byp,” etc.), namely enable signals used to control the latches in the transform architecture of Figure 141, and therefore control signal flow. Wise, col. 262, ll. 55-65; col. 266, ll. 38-67; col. 267, ll. 7-48. Wise’s 1D Transform Micro-Architecture in Figure 141 is reproduced below: Figure 11 and the corresponding description of the SCD which (1) detects MPEG, JPEG, and H.261 start codes in the input stream, and (2) replaces them with tokens. See Wise, col. 195, ll. 13-26. Nevertheless, we deem Appellants’ error in this regard harmless. 4 Although Wise repeatedly refers to Figure 138 in connection with the IDCT block diagram in Section B.9.8 in columns 263 and 264, Figure 139 actually shows the block diagram described in that section. Appeal 2011-001062 Application 09/997,530 7 Wise’s 1D Transform Micro-Architecture in Figure 141 As shown above, the control signals “latch,” “sel_byp,” “add/sub,” the multiplexer control signals, etc. are not part of—nor directed to—the “common block,” but rather outside that block. So even assuming that these control signals configure interconnections between associated components to perform basic computational and complex processing functions, they do so outside the “common block”: a feature diametrically opposite to the Examiner’s position which maps the recited interconnection networks to components inside the “common block.” See Ans. 4, 17-20, 22-25. That the textual note on Wise’s Figure 141 indicates that the “common block” is entirely combinational with no latching only bolsters our conclusion that the interconnections within the “common block” are not configurable via latches or otherwise, but rather fixed connections. Nevertheless, to the extent that the control signals and associated circuitry on both sides of the “common Appeal 2011-001062 Application 09/997,530 8 block” could correspond to the recited interconnection networks 5 is a position that has not been articulated on this record; nor will we engage in that inquiry here in the first instance on appeal. What we can say, however, is that the Examiner’s position that the recited interconnection networks are in the “common block” is untenable. That said, the Examiner makes an interesting point regarding Wise’s reconfigurable process stage (RPS) (Ans. 18-19, 25): a stage that reconfigures itself responsive to a recognized token to perform various operations. Wise, Abstract; col. 12, ll. 45-47; col. 37, ll. 23-41; col. 52, l. 20 – col. 55, l. 34; Fig. 10. Despite this reconfigurability—a key aspect of Wise’s system for selected stages as noted in the Abstract—we agree with Appellants to the extent that Wise does not explicitly indicate that the interconnections associated with the IDCT are reconfigurable via an RPS. Reply Br. 7-8. 6 That all IDCT blocks ignore control tokens as noted above only bolsters the conclusion that the IDCT is not reconfigurable via these tokens—a key aspect of the RPS function. See Wise, col. 263, ll. 40-44, 60- 62; col. 264, ll. 21-24 (block 443), 41-45 (block 445); Abstract (noting that reconfigurable processing circuits are positioned in selected stages and 5 Although Appellants acknowledge that Wise’s latches route data to certain computational elements (App. Br. 16; Reply Br. 8), the Examiner has not shown that this routing teaches or suggests configuring interconnections between those elements as claimed. Nor will we speculate in that regard here in the first instance on appeal. 6 Although Appellants repeatedly argue that Wise does not anticipate the claims (App. Br. 14-16, Reply Br. 1, 8), that is not the standard under § 103 which is based on obviousness—not anticipation. Nevertheless, we deem Appellants’ errors in this regard harmless. Appeal 2011-001062 Application 09/997,530 9 responsive to a recognized control token to reconfigure that stage to handle an identified DATA token). Nevertheless, to the extent that it would have been obvious to modify Wise’s IDCT—a function whose transform blocks have a pipeline depth of 20 stages and control sections (Wise, col. 266, ll. 38-67)—to reconfigure interconnections between associated components to perform basic computational and complex processing functions via RPS has not been articulated on this record. Nor has the Examiner shown that this improvement predictably uses prior art elements according to their established functions. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). And while it is clear that Wise’s RPS function improves the system by automatically reconfiguring certain stages of the system, to the extent that ordinarily skilled artisans would recognize that RPS would improve similar stages—such as IDCT stages—in the same way (see id.) is a position that has likewise not been articulated on this record. Nor will we speculate in that regard here in the first instance on appeal. We are therefore persuaded that the Examiner erred in rejecting (1) independent claim 182; (2) independent claims 213, 246, and 276 which recite commensurate limitations; and (3) the dependent claims for similar reasons. THE OTHER REJECTION Since the Examiner has not shown that Cohen cures the deficiencies noted above regarding the independent claims, we will not sustain the obviousness rejection of claims 247 and 277 (Ans. 16-17) for similar reasons. Appeal 2011-001062 Application 09/997,530 10 CONCLUSION The Examiner erred in rejecting claims 182-305 under § 103. ORDER The Examiner’s decision rejecting claims 182-305 is reversed. REVERSED kis