Ex Parte Manning

Patent Trial and Appeal BoardAug 9, 2017

13184168 (P.T.A.B. Aug. 9, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/184,168 07/15/2011 Troy A. Manning 303.A51US2 9827 73115 7590 08/11/2017 SCHWEGMAN LUNDBERG & WOESSNER/MICRON P.O. BOX 2938 MINNEAPOLIS, MN 55402 EXAMINER NGUYEN, VAN THU T ART UNIT PAPER NUMBER 2824 NOTIFICATION DATE DELIVERY MODE 08/11/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): uspto@slwip.com SLW @blackhillsip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte TROY A. MANNING Appeal 2017-000651 Application 13/184,168 Technology Center 2800 Before GEORGE C. BEST, JEFFREY R. SNAY, and DEBRA L. DENNETT, Administrative Patent Judges. SNAY, Administrative Patent Judge. DECISION ON APPEAL1 Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner’s decision rejecting claims 1—19. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We cite the Specification (“Spec.”) filed July 15, 2011; Final Office Action (Final Act.) dated May 28, 2015; Appellants’ Appeal Brief (“App. Br.”) dated January 11, 2016; Examiner’s Answer (“Ans.”) dated August 4, 2016, and Appellants’ Reply Brief (“Reply Br.”) dated October 4, 2016. 2 Appellant identifies Micron Technology, Inc. as the real party in interest. App. Br. 2. Appeal 2017-000651 Application 13/184,168 BACKGROUND The subject matter on appeal relates to a method and apparatus for accessing a portion of a row of a memory array. Spec. Abstract. Claim 1 illustrates the subject matter involved in this appeal, and is reproduced from the Substitute Claims Appendix of the Appeal Brief as follows:3 1. A method comprising: a mask generator receiving a row address of a memory array, a column address of the memory array, and an amount of data to access in the memory array, the memory array having a row corresponding to the row address, the row having a plurality of memory cells; the mask generator generating a row mask address for accessing one or more memory cells of the row without accessing all the memory cells of the row; and the mask generator providing, to the memory array coupled to the mask generator, the row mask address to access memory cells of the row. REJECTIONS The Examiner maintains the following grounds of rejection:4 I. Claims 1—4 stand rejected under 35 U.S.C. § 112, second paragraph. II. Claims 1—18 stand rejected under 35 U.S.C. § 102(b) as anticipated by Jungroth.5 III. Claim 19 stands rejected under 35 U.S.C. § 103(a) as unpatentable over Jungroth. 3 Appellant submitted a Substitute Claims Appendix on May 26, 2016. 4 Final Act. 2—9; Ans. 2—9. 5 US 5,621,690, issued April 15, 1997 (“Jungroth”). 2 Appeal 2017-000651 Application 13/184,168 DISCUSSION Rejection I With regard to Rejection I, the Examiner finds that claim 1 is directed to a method but fails to set forth any method step, and determines each of claims 1—4 to be indefinite on that basis. Final Act. 2—3. Appellant argues that claim 1 recites three method steps—receiving, generating, and providing—each of which is performed by a mask generator. App. Br. 6; Reply Br. 2. We agree. See, e.g., claim 1 (“a mask generator receiving a row address of a memory array”). Rejection I is not sustained. Rejection II With regard to Rejection II, Appellant argues the claims as a group, focusing solely on claim 1. App. Br. 6—8. In accordance with 37 C.F.R. § 41.37(c)(l)(iv), we select claim 1 as representative. Each of claims 2—18 stands or falls with the representative claim. As is relevant to Appellant’s arguments on appeal, the Examiner finds that Jungroth describes a method which, referring to Jungroth’s Figure 3, includes steps of generating and providing block selection signals BSO through BSn using a block decoder 37, so as to access some but not all blocks of memory cells in a memory array. Final Act. 4. The Examiner equates Jungroth’s block selection signals with the claimed row mask address. Ans. 9—10 (“[T]he decoded block address signals BSO-BSn are seen as the claimed row mask address.”). The Examiner also finds that Jungroth’s block decoder 37 receives “an amount of data to be accessed” in the form of block address data received from bus 43, concerning identification of which blocks in the array are to be addressed and which are not. Id. at 11 (citing Jungroth 7:61—65). 3 Appeal 2017-000651 Application 13/184,168 Appellant argues that Jungroth’s block decoder generates control signals which represent a particular decoded address, not an address. App. Br. 7. However, Appellant fails to materially distinguish between the recited mask address and control signals representative of a mask address. Moreover, Appellant’s argument is inconsistent with the Specification’s description of the mask generator’s output as “signals to the memory array to access the memory cells.” Spec. 133 (emphasis added); see, also, id. Fig. 4 (depicting the mask generator output as signals). Appellant does not dispute that Jungroth’s block decoder provides signals to the memory array for selectively accessing blocks of memory cells. On this appeal record, we are not persuaded of reversible error in the Examiner’s finding that the “row mask address for accessing one or more memory cells” recited in claim 1 encompasses Jungroth’s block decoder signals for selectively accessing memory cells. Appellant also argues that Jungroth’s block decoder does not receive “an amount of data to access in the memory array,” as is recited in claim 1. App. Br. 7. Particularly, Appellant contends that Jungroth’s block decoder receives address information from bus 43 and control signals from comparison logic 40, which the block decoder uses to identify and replace defective memory cell blocks with corresponding redundant blocks. Id. at 7—8. The Examiner finds that the above-mentioned information which is received by Jungroth’s block decoder constitutes an amount of data to access in the memory array. Final Act. 3^4. Because Appellant fails to persuasively explain why data corresponding to which memory cell blocks to access does not constitute “an amount of data to access in the memory,” 4 Appeal 2017-000651 Application 13/184,168 we are not persuaded of reversible error in the Examiner’s finding that Jungroth’s block decoder receives an amount of data as recited in claim 1. For the foregoing reasons, we sustain Rejection II as to each of claims 1-18. Rejection III Appellant does not separately argue against Rejection III, other than an implicit reliance on the arguments presented in connection with Rejection II. Accordingly, we also sustain Rejection III as to claim 19. DECISION The Examiner’s decision rejecting claims 1—19 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136. AFFIRMED 5