Ex Parte Liang et al

Patent Trial and Appeal Board

Dec 29, 2016

13085745 (P.T.A.B. Dec. 29, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/085,745 04/13/2011 Shih-Wei LIANG T5057-R392 2717
95496 7590 01/03/2017
Hauptman Ham, LLP (TSMC)
2318 Mill Road
Suite 1400
Alexandria, VA 22314
EXAMINER
MIYOSHI, JESSE Y
ART UNIT PAPER NUMBER
2896
NOTIFICATION DATE DELIVERY MODE
01/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tsmc@ipfirm.com
sramunto @ ipfirm.com
pair_lhhb @ firsttofile. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHIH-WEI LIANG, YU-WEN LIU, and HSIEN-WEI CHEN
Appeal 2015-008208
Application 13/085,745
Technology Center 2800
Before BEVERLY A. FRANKLIN, GEORGE C. BEST, and
JEFFREY R. SNAY, Administrative Patent Judges.
FRANKLIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants request our review under 35 U.S.C. § 134 of the
Examiner’s decision rejecting claims 1—3, 5—14, and 16—20. We have
jurisdiction over the appeal under 35 U.S.C. § 6(b).
STATEMENT OF THE CASE
Claim 1 is illustrative of Appellants’ subject matter on appeal and is
set forth below (with text in bold for emphasis):
1. An integrated circuit comprising:
a first substrate;
a functional circuit comprising:
Appeal 2015-008208
Application 13/085,745
a semiconductor device formed on the first
substrate;
a first wiring stack formed on the first substrate,
the first wiring stack electrically connected to the
semiconductor device;
a first set of bond pads formed on the first wiring
stack; and
a first set of bump balls, each bump ball of the first
set of bump balls formed on a corresponding bond pad of
the first set of bond pads; and a test circuit comprising:
a second wiring stack formed on the first substrate,
the second wiring stack electrically separated from the
semiconductor device;
a second set of bond pads formed on the second
wiring stack;
a second set of bump balls, each bump ball of the
second set of bump balls formed on a corresponding
bond pad of the second set of bond pads, and the second
set of bump balls being dummy bump balls;
a first electrical connection between at least two
bump balls of the second set of bump balls;
a second substrate bonded to the first substrate; and
a second electrical connection between the second
substrate and the at least two bump balls of the second set
of bump balls.
The Examiner relies on the following prior art references as evidence
of unpatentability:
Jao
Su
Kudo
US 7,256,475 B2
US 7,622,309 B2
US 2009/0315029 A1
Aug. 14, 2007
Nov. 24, 2009
Dec. 24, 2009
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Appeal 2015-008208
Application 13/085,745
THE REJECTIONS
1. Claim 5 is rejected under 35 U.S.C. § 112, second paragraph, as being
indefinite.1
2. Claims 1—3, 5—14, and 16—20 are rejected under pre-AIA 35 U.S.C.
§ 103(a) as being unpatentable over Kudo in view of Jao and Su.
ANALYSIS
Rejection 2
We reverse Rejection 2 based upon Appellants’ presented arguments
and evidence in the record. We add the following for emphasis only.
Appellants argue, inter alia, that, contrary to the Examiner’s
interpretation of Kudo, Kudo does not suggest the claim elements pertaining
to “a first wiring stack formed on the first substrate, the first wiring stack
electrically connected to the semiconductor device” and “a second wiring
stack formed on the first substrate, the second wiring stack electrically
separated from the semiconductor device”. Appeal Br. 11—17. Reply Br. 2—
8. We are in full agreement with Appellants’ stated position for the reasons
presented in the record (which we adopt as our own and do not repeat
herein). For those reasons presented by Appellants, we cannot agree with
the Examiner that connection wire 11 of Kudo cannot be connected to the
circuitry of the functional elements of logic chip 70 (Ans. 4—5), and that
1 We summarily affirm Rejection 1 because Appellants do not contest this
rejection in the Appeal Brief or in the Reply Brief. See Appeal Brief or in
the Reply Brief, generally. Cf. Hyatt v. Dudas, 551 F.3d 1307, 1314 (Fed.
Cir. 2008) (explaining that an appeal of ground of rejection is waived when
an appellant fails to contest the rejection and that the Board is free to affirm
such an uncontested rejection without considering the merits).
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Appeal 2015-008208
Application 13/085,745
2c(BSHTl) and 2c(BSHT2) have different electrical connections than other
elements 2c {id. at 6). As such, we are persuaded that the aforementioned
claim elements are not suggested by Kudo. The Examiner does not rely
upon Jao and Su to cure the stated deficiencies of Kudo in this regard. We
thus reverse Rejection 2.
DECISION
Rejection 1 is summarily affirmed (see footnote 1, supra).
Rejection 2 is reversed.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a).
ORDER
AFFIRMED-IN-PART
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