Ex Parte Lewis et al

Patent Trial and Appeal BoardOct 29, 2012

10544749 (P.T.A.B. Oct. 29, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte JODY WESTERN LEWIS and KERRY LYNN RIGGS ____________ Appeal 2010-005088 Application 10/544,749 Technology Center 2100 ____________ Before ERIC S. FRAHM, KALYAN K. DESHPANDE, and JOHNNY A. KUMAR, Administrative Patent Judges. KUMAR, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-005088 Application 10/544,749 2 I. STATEMENT OF THE CASE1 Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1-15. We have jurisdiction under 35 U.S.C. § 6(b). We affirm the Examiner’s rejection of these claims. Appellants’ Invention Appellants’ invention relates to a technique for achieving synchronous serial communication between devices. Spec. 1: 5-6. An understanding of the invention can be derived from a reading of exemplary claim 1, which is reproduced below [bracketed matter added]: 1. A method for facilitating asynchronous serial communication by a main processor with at least one external communications device, comprising the steps of: [a] establishing at the main processor a set of blocks of instructions each including at least one instruction for execution by the main processor for accomplishing serial communication, each block having at least one task initiated by at least one instruction, the at least one task running at a prescribed priority, such that the tasks of different blocks have a hierarchical priority; [b] determining whether higher priority tasks are present in the blocks of instructions to be executed, [c] executing the blocks of instructions so that at least one task within each block runs at its respective priority level; and [d] triggering each higher priority task upon completion of a corresponding lower priority task; 1 Our decision will make reference to the Appellants’ Appeal Brief (“App. Br.,” filed Jul. 20, 2009) and Reply Brief (“Reply Br.,” filed Dec. 22, 2009), and the Examiner’s Answer (“Ans.,” mailed Oct. 27, 2009). Appeal 2010-005088 Application 10/544,749 3 [e] wherein said executing and triggering is performed for lower priority tasks only when it is determined that higher priority tasks are present in the blocks of instructions to be executed. Prior Art Relied Upon Adkins US 5,247,671 Sep. 21, 1993 Carter US 4,800,521 Jan. 24, 1989 Rejection on Appeal Claims 1-15 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Adkins in view of Carter. Ans. 3-9. II. ISSUE The issue of whether the Examiner erred in rejecting claims 1-15 turns on whether the combination of Adkins and Carter teaches or suggests “triggering each higher priority task upon completion of a corresponding lower priority task,” as set forth by limitation [d] in claim 1; and “wherein said executing and triggering is performed for lower priority tasks only when it is determined that higher priority tasks are present in the blocks of instructions to be executed,” as set forth by limitation [e] in claim 1. III. ANALYSIS We have reviewed the Examiner’s rejection in light of the Appellants’ contentions that the Examiner has erred. We disagree with the Appellants’ conclusions. We adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons set forth by the Examiner in Appeal 2010-005088 Application 10/544,749 4 the Examiner’s Answer in response to the Appellants’ Appeal Brief. We concur with the conclusion reached by the Examiner. We highlight the following arguments for emphasis. 35 U.S.C. § 103(a) Rejection—Adkins and Carter Claims 1, 8, and 12 Appellants contend that Adkins and Carter fail to “disclose or render obvious performing a low priority task only when it is determined that higher priority tasks are present in instruction execution blocks.” App. Br. 10-11. Appellants also contend that Carter “merely states that unrelated low priority tasks may be performed between high priority tasks in a way that maintains execution speed and minimizes any delay in the execution of the high priority tasks.” Reply Br. 8 (emphasis ours). In particular, Appellants contend that Carter “intermingles performance of a low priority task between performances of high priority tasks.” App. Br. 10; Reply Br. 8. The Examiner relies upon Carter for teaching a system that executes low priority tasks after determining that high priority tasks have been executed at least once (Ans. 9). In particular, the Examiner points to the disclosure of the Scheduler Manager 102 in Carter and explains (Ans. 9-11, citing col. 11, ll. 59 to col 12, ll. 4, and Fig 7) that the Scheduler Manager 102 first executes the high priority tasks e.g., Task 212, then Task 81, and then Task 150 and the other tasks in the high priority section ending with Task 6. Thereafter, the Scheduler Manager 102 executes the next task in sequence in the low priority section, e.g. Task 231. After executing Task 231, the control returns to the high priority section with Task 212 to the last Appeal 2010-005088 Application 10/544,749 5 task, Task 6. The control then jumps to the low priority section, but this time to Task 12, the next task after the previously executed Task 231. The Examiner finds that the element recited in claim 1[d] is met by the execution of Task 212 then Task 81, Task 150 and other tasks in the high priority section ending with Task 6 upon completion of the lower priority tasks (Task 231) of Carter. Ans. 10. The Examiner also finds that the element recited in claim 1[e] is met by the execution of lower priority tasks (task 231) that is performed after determining that higher priority tasks (Tasks 212, 81, 150, and 6) are present in the blocks of instructions to be executed. Id. As to Appellants’ contentions that Carter describes “unrelated” and the “intermingling” low priority tasks that may be performed between high priority tasks, Appellants’ arguments are not commensurate with the scope of the claim. The claims are given their broadest reasonable construction in light of the disclosure. See In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Also, we find that the limitation “corresponding” is sufficiently broad such that it encompasses the performance of a low priority task between performances of high priority tasks, as described by Carter. Finally, Appellants do not point to anything in the claims or Specification or present persuasive evidence or argument that precludes this interpretation. See App. Br. 8-11. We note that Appellants’ arguments in the Reply Brief center on a “requiring a multiprocessor system”and Carter “teaches away from the system and method of the present principles.” Reply Br. 6-8. As this argument was made for the first time in the Reply Brief, it is waived. See Ex Appeal 2010-005088 Application 10/544,749 6 parte Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (“informative”2) (absent a showing of good cause, the Board is not required to address argument in Reply Brief that could have been presented in the principal Brief). Claims 2-7, 9-11, and 13-15 The Appellants contend that dependent claims 2-7, 9-11, and 13-15 are patentable for the same reasons asserted in support of claims 1, 8, and 12, respectively. App. Br. 7. The Appellants’ arguments were not found to be persuasive supra and are not persuasive here for the same reasons. IV. CONCLUSION The Examiner has not erred in rejecting claims 1-15 as being unpatentable under 35 U.S.C. § 103(a). V. DECISION We affirm the Examiner’s decision to reject claims 1-15. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED msc 2 The “informative” status of this opinion is noted at the following Board website: http://www.uspto.gov/ip/boards/bpai/decisions/inform/index.jsp.