Ex Parte Leibowitz

Patent Trial and Appeal BoardMay 26, 2017

11958514 (P.T.A.B. May. 26, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/958,514 12/18/2007 Robert N. Leibowitz M3400.625.101 1235 128996 7590 05/31/2017 DICKE, BILLIG & CZAJA - MICRON 100 S 5TH ST STE 2250 MINNEAPOLIS, MN 55402 EXAMINER VERDERAMO III, RALPH A ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 05/31/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): USPTO.PATENTS @dbclaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ROBERT N. LEIBOWITZ Appeal 2017-003488 Application 11/958,514 Technology Center 2100 Before JOSEPH L. DIXON, JAMES R. HUGHES, and MICHAEL J. STRAUSS, Administrative Patent Judges. DIXON, Administrative Patent Judge. DECISION ON APPEAL Appeal 2017-003488 Application 11/958,514 STATEMENT OF THE CASE Appellant appeals under 35 U.S.C. § 134 from a rejection of claims 1— 27. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. The invention relates to an address translation system for a non volatile memory device, such as a flash memory (Spec, 11—12). The non volatile memory device includes a memory array and a memory controller, and the memory controller is connected via a serial data bus to an external memory device, such as a DRAM {id. ]Hf 14, 16—17). The external memory device also includes a standard memory interface to communicate with other devices {id. 116). In one embodiment, the memory controller may receive a command, such as a read or write operation, that includes a logical address, and then uses the external memory device to lookup, in an address translation table, a corresponding physical address for the logical address to perform the operation {id. H 18—19). Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. An address translation system comprising: a non-volatile memory device comprising a memory controller and a memory array; an external memory device, separate from the non-volatile memory device, for storing address translation data accessible by the memory controller over a dedicated serial data bus between and coupled to the memory controller and the external memory device; and an interface separate from the dedicated serial data bus and coupled to the external memory device in addition to the dedicated serial data bus being coupled to the external memory device; 2 Appeal 2017-003488 Application 11/958,514 wherein the external memory device communicates over the interface using a parallel format and communicates over the dedicated serial data bus using a serial format. REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Yoshida Chou Kikuchi Ohara US 2004/0145939 A1 US 6,874,044 B1 US 2006/0143365 A1 US 2006/0200614 A1 July 29, 2004 Mar. 29, 2005 June 29, 2006 Sept. 7, 2006 Michael T. Moore, “The Advantages and Disadvantages of Serial Links in Communication system Design” (June 20, 2002) (hereinafter “NPL1” (Non- Patent Literature 1)) Webopedia, “DRAM Memory Guide: A Quick Reference to System Memory” (January 14, 2005) (hereinafter “NPL2”) Webopedia, “Different Types of Memory Cards” (October 5, 2007) (hereinafter “NPL3”) REJECTIONS The Examiner made the following rejections: Claims 1—3, 5—7, 9, 10, 13—17, and 27 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, and Chou. Claims 4, 8, 11, and 18—20 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, Chou, and NPL2. Claim 12 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, Chou, NPL2, and NPL3. Claim 21 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, Chou, NPL2, and Ohara. 3 Appeal 2017-003488 Application 11/958,514 Claims 22—25 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, Chou, and Yoshida. Claim 26 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Kikuchi, NPL1, Chou, NPL2, and Official Notice. ANALYSIS Appellant contends that it would not have been obvious to use different communication formats—serial and parallel—for the two ports of Chou’s RAM buffer 34 in the combined system of Kikuchi and Chou, despite NPL1 ’s teaching that serial and parallel communication formats have respective advantages and disadvantages (see App. Br. 12—17). Specifically, Appellant argues the Examiner failed to show it would have been obvious to try using two different communication formats because the Examiner did not articulate a recognized problem or need in the art at the time of the invention (App. Br. 14—15; Reply Br. 2—5). Rather, Appellant argues there is a contrary motivation to use the same communication format for both ports of Chou’s RAM buffer 34 (App. Br. 16). We are not persuaded by Appellant’s arguments. The Examiner relies on Kikuchi’s flash memory 11 and CPU 121 for disclosing the “memory array” and “memory controller” of the “non-volatile memory device” recited in claim 1, and RAM 123 for disclosing the “external memory device,” as further recited in claim 1 (Final Act. 3; Kikuchi, Fig. 1). The Examiner further relies on Chou’s RAM buffer 34 for teaching an external memory device with two ports (Final Act. H 4—5; Chou, Fig. 4). The Examiner concludes, based on NPL1 ’s disclosure of certain respective advantages of serial and parallel data buses, that it would have been obvious to use a serial format for communicating through the first 4 Appeal 2017-003488 Application 11/958,514 port of the RAM in the combined system of Kikuchi and Chou, and a parallel format for communicating through the second port of the RAM (see Final Act. 4; Ans. 27). We agree with the Examiner for the following reasons. NPL1 lists some advantages of serial buses, including “serial links can drive longer distance than parallel buses and are less susceptible to noise,” “[cjircuit board routing is simpler, as only two serial lines need to be routed, replacing a wide bus,” “[fjewer connector pins are used, improving board area utilization and reliability,” and “[p]oint-to-point links have greater efficiency than shared buses like PCI” (NPL1, p. 4). NPL1 also lists some advantages of parallel buses, including “[pjarallel buses, in particular PCI, are very widely deployed and abundant cheap silicon is available,” “[m]any engineers are experienced in designing PCI parallel buses,” and [tjhere is a widely installed base of PCI-compatible equipment and software” (id.). In view of these respective advantages, we find it would have been obvious to one of ordinary skill in the art to try using a serial format and a parallel format for two different ports of a RAM because there are only four combinations for a RAM with two ports, such as in the combined system of Kikuchi and Chou: both ports serial; both ports parallel; first port serial and second port parallel; and first port parallel and second port serial. We are not persuaded by Appellant’s argument that the Examiner failed to show it would have been obvious to try the claimed solution because the Examiner has not identified a recognized problem or need to solve by trying different solutions (App. Br. 14—15; Reply Br. 2—5). Here, the design need is self-evident: in a system design where a RAM has two ports, as in the combined system of Kikuchi and Chou, there is a need to define a format for actually communicating over the ports. The limited 5 Appeal 2017-003488 Application 11/958,514 number of four solutions noted above would have invited one of ordinary skill in the art to try each of the solutions to find the optimal design. In other words, for each port on a RAM, a designer would need to decide how to make the port work, and where there are only two general formats available—serial and parallel—each with respective advantages, the designer would be motivated to try both formats to see which worked best for that particular port. That is, “[w]hen there is a design need ... to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp.” KSRInt’l Co. v. Teleflex Inc., 550 U.S. 421 (2007). Appellant’s argument that the references suggest using the same format for both interfaces of the external memory device is also not persuasive (see App. Br. 15—17). The fact that one solution may have led to a successful design would not have precluded one of ordinary skill in the art from also trying other solutions where, as in this case, there are a limited number of predictable solutions. We are, therefore, not persuaded the Examiner erred in rejecting claim 1, and claims 2—27 not specifically argued separately. CONCLUSION The Examiner did not err in rejecting claims 1—27 under 35 U.S.C. § 103(a). DECISION For the above reasons, the Examiner’s rejection of claims 1—27 is affirmed. 6 Appeal 2017-003488 Application 11/958,514 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 7