Ex Parte Le Grand

Patent Trial and Appeal Board

Sep 17, 2012

11610373 (P.T.A.B. Sep. 17, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/610,373 12/13/2006 Scott Le Grand 019680-030500US 2652
45890 7590 09/17/2012
KILPATRICK TOWNSEND & STOCKTON LLP
(NVIDIA)
TWO EMBARCADERO CENTER
8TH FLOOR
SAN FRANCISCO, CA 94111-3834
EXAMINER
KRAMER, JAMES A
ART UNIT PAPER NUMBER
3621
MAIL DATE DELIVERY MODE
09/17/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte SCOTT LE GRAND
____________________

Appeal 2011-000237
Application 11/610,373
Technology Center 3600
____________________

Before: JOSEPH A. FISCHETTI, MEREDITH C. PETRAVICK, and
MICHAEL W. KIM, Administrative Patent Judges.

KIM, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-000237
Application 11/610,373

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STATEMENT OF CASE
Appellant seeks our review under 35 U.S.C. § 134 from the
Examiner’s final rejection of claims 1, 2, 4-7, 9-11, and 17-221. We have
jurisdiction under 35 U.S.C. § 6(b).

SUMMARY OF THE DECISION
We affirm.

BACKGROUND
Appellant’s invention is directed to performing binomial options
pricing model computations using graphics processors (Spec., para. [0001]).
Claim 1 is illustrative:
1. A method for performing binominal options pricing
model computations using a processor having a plurality of
processing engines that are operable in parallel and coupled to a
shared memory, the method comprising:
reading, by one or more of the processing engines, a first
swath of a set of node values from an external memory into the
shared memory;
executing, by each of at least two of the plurality of
processing engines in parallel, a sequence of binomial options
pricing model computations corresponding to a plurality of time
steps to generate a set of results,
wherein the execution of each binomial options pricing
module computation in the sequence includes:
reading two of the node values from the shared
memory;
computing a new node value corresponding to a
next time step from the two node values read from the
shared memory; and

1 Our decision will make reference to Appellant’s Appeal Brief (“App. Br.,”
filed Apr. 5, 2010) and Examiner’s Answer (“Ans.,” mailed Jun. 22, 2010).
Appeal 2011-000237
Application 11/610,373

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writing the new node value to the shared memory;
and
storing, by one or more of the processing engines, the set
of results in an external memory.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Garman
Makivic
US 5,692,233
US 6,061,662
Nov. 25, 1997
May 9, 2000

Appellant appeals the following rejection: Claims 1, 2, 4-7, 9-11, and
17-22 are rejected under 35 U.S.C. § 103(a) as unpatentable over Makivic
and Garman.

ISSUE
The issue of obviousness turns on whether Makivic or Garman
disclose the use of both “shared” and “external” memory.

FACTUAL FINDINGS
We find the following facts by a preponderance of the evidence.
1. Makivic discloses the use of “shared memory” in a computing system.
(Col. 12, ll. 41-43).
2. Makivic discloses the use of “external memory” as distributed memory
that is part of networked workstations that are part of a parallel
computing implementation. (Col. 12, ll. 43-45).
3. Makivic discloses reading values from, and storing results to, external
memory, at initialization and when averages from different processors are
combined into a single estimate. (Col. 13, ll. 5-8).
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Application 11/610,373

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4. Garman discloses writing results to mass storage unit 18 upon
termination of a simulation. (Col. 8, ll. 5-10).
5. Garman discloses a preferred embodiment that comprises a central
processing unit 10, memory means 16, and mass storage 18. (Col. 2, ll.
59-62).

ANALYSIS
As Appellant argues all pending claims as a group (App. Br. 5), we
select claim 1 as representative, and all other claims stand or fall with claim
1. See, 37 C.F.R. § 41.37(c)(1)(vii).
The Specification does not define the claimed “shared” and “external”
memory. The Specification describes by example that graphics processors
may off-load the work of a central processor (Spec., para. [0003]), using
parallel processors on the graphics card, each processor having on-chip
memory (Spec., para. [0007]). The Specification also describes by example
“external memory” as meaning memory external to this memory-containing,
parallel graphics card, such as main system memory (Spec., para. [0005]-
[0006]). However, the claim does not limit the implementation to graphics
cards, but also includes other implementations and architectures, as
described by the Specification (Spec., para. [0005]). We therefore broadly
construe “external memory” to be a data storage apparatus external to the
microprocessor/memory system doing computations, which memory
encompasses memory in external, interconnected systems, and also external
disk storage local to the computing system processors.
Based on this claim construction, we are not persuaded by Appellant’s
argument that the combination of Makivic and Garman does not disclose
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two levels of memory, both shared and external, as claimed. (App. Br. 5-7).
Makivic discloses shared memory explicitly (FF 1), and also discloses the
use of “external” memory, both as “distributed memory” and as memory in
“networked workstations” which are external to the shared memory systems
(FF 2). Makivic discloses reading values from external memory at the
initialization stage, and storing the set of results in an external memory upon
termination of the simulation, by communicating with external processors
(FF 3).
In addition, Garman discloses writing results to “external memory” at
mass storage 18 (FF 4), which is external to the central processing unit 10
and memory 16 (FF 5). Therefore, the Garman disclosure is cumulative.

DECISION
We affirm the rejection of claims 1, 2, 4-7, 9-11, and 17-22 under 35
U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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