Ex Parte LarsonDownload PDFPatent Trial and Appeal BoardJan 9, 201311125767 (P.T.A.B. Jan. 9, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD _____________ Ex parte THANE M. LARSON _____________ Appeal 2010-006811 Application 11/125,767 Technology Center 2800 ______________ Before: ROBERT E. NAPPI, JUSTIN BUSCH, and LYNNE E. PETTIGREW, Administrative Patent Judges. NAPPI, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-006811 Application 11/125,767 2 This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection of claims 9, 11 through 16, and 19 through 22. We affirm. INVENTION The invention is directed to a system which detects and corrects errors in data stored in memory. The system makes use of horizontal and vertical error correcting codes. Specification paragraphs 15 and 16. Claim 12 is representative of the invention and reproduced below: 12. A memory module, comprising: a plurality of memory devices, each memory device operable to store data in a plurality of memory locations arranged in rows and columns; and error logic coupled to the memory devices, the logic operable according to a specified parameter to automatically to generate a vertical error correcting code for each column of memory locations on the memory module and to store each vertical error correcting code in the memory devices, and operable to automatically detect and correct errors in any of the columns of memory locations using the corresponding vertical error correcting codes, and the error logic further operable responsive to detecting an error that cannot be corrected in a column of memory locations to provide a notification signal adapted to cause external horizontal scrubbing of the memory locations in the memory devices; wherein each memory device comprises a DRAM and wherein the specified parameter is a dedicated refresh cycle of the DRAMs. REFERENCES Price US 5,418,796 May 23, 1995 Nguyen US 6,279,135 B1 Aug. 21, 2001 Hwang US 2003/0145274 A1 Jul. 31, 2003 Appeal 2010-006811 Application 11/125,767 3 Klein US 2003/0191888 A1 Oct. 9, 2003 Appellant’s admitted prior art. REJECTIONS AT ISSUE The Examiner has rejected claims 9, 11 through 16, and 19 through 20 under 35 U.S.C. § 103(a) as unpatentable over Klein in combination with either Hwang or Nguyen. Answer 3-8.1 The Examiner has rejected claim 22 under 35 U.S.C. § 103(a) as unpatentable over Klein and Appellant’s admitted prior art in combination with either Hwang or Nguyen. Answer 8-9. The Examiner has rejected claim 21 under 35 U.S.C. § 103(a) as unpatentable over Klein in combination with either Hwang or Nguyen, and in further combination with either Appellant’s admitted prior art or Price. Answer 9-10. ISSUES Appellant argues on pages 8 through 12 of the Brief that the Examiner’s rejection of claims 9, 11 through 16, and 19 through 20 under 35 U.S.C. § 103(a) based upon the teachings of Klein, Hwang, and Nguyen, is in error.2 These contentions present us with two issues: a) Did the Examiner err in not considering Klein to teach away from the combination of the references? 1 Throughout this opinion we refer to the Examiner’s Answer mailed on November 12, 2009. 2 Throughout this opinion we refer to the Appeal Brief dated August 3 and Reply Brief filed January 12, 2010. Appeal 2010-006811 Application 11/125,767 4 b) Did the Examiner err in finding that Klein teaches a dedicated refresh cycle of the DRAM as claimed? Appellant’s arguments directed to the rejections of claims 21 and 22, on page 13 and 14 of the Brief present us with the same issues. ANALYSIS We have reviewed Appellant’s arguments in the Brief, the Examiner’s rejection and the Examiner’s response to Appellant’s arguments. We disagree with Appellant’s conclusion that the Examiner erred in: not considering Klein to teach away from the combination of the references; and finding that Klein teaches a dedicated refresh cycle of the DRAM. With respect to the first issue, Appellant asserts that Klein teaches that data errors cannot occur in a normal operating mode and the check bits are only performed when transitioning to the power saving mode. Brief 8-9. Appellant argues that this teaches away from combining Klein with Nguyen or Hwang, which both teach that errors occur during a normal mode. Brief 11. The Examiner provides a comprehensive response to Appellant’s arguments on pages 10 through 12 of the Answer. In this response the Examiner identifies: the claims are not drawn to one particular mode of operation; that Appellant’s statement that Klein teaches errors cannot occur in normal mode is a mischaracterization of Klein’s teaching; and the combination used to reject the claims is applying Hwang and Nguyen’s teaching of error correction to Klein’s reduced power mode. Answer 11-12. We concur with the Examiner’s rationale and adopt it as our own. The Examiner, in the rejection, on pages 4 and 5 of the Answer, finds that Klein Appeal 2010-006811 Application 11/125,767 5 is silent on the particulars of the error techniques and that the secondary references, to Hwang and Nguyen, teach these techniques. Appellant’s arguments have not persuaded us that the skilled artisan would be discouraged from using the error correction techniques of Hwang and Nguyen in Klein’s device just because Klein uses the error correction when operating in a different mode. As such, we do not find that Klein teaches away from the combination.3 Thus, Appellant’s arguments directed to the first issue have not persuaded us of error in the Examiner’s rejection under 35 U.S.C. § 103(a) based upon the teachings of Klein, Hwang, and Nguyen. With respect to the second issue, the Examiner finds Klein teaches that in the power save mode the low scrubbing rate refreshes the memory cells, which meets the claimed dedicated refresh cycle as the entire memory is refreshed. Answer 13. We concur with the Examiner’s findings as they are supported by ample evidence. We are not persuaded by Appellant’s argument that Klein’s dedicated operation is not a dedicated refresh cycle as it does not refresh all of the memory (Reply Brief 10) because the Examiner 3 We note that on pages 3 through 8 of the Reply Brief, Appellant argues that the combination changes the principle of operation of Hwang and Nguyen. These arguments were presented for the first time in the Reply Brief and have not been considered as they are deemed waived. See Ex parte Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (“informative”) (absent a showing of good cause, the Board is not required to address argument in Reply Brief that could have been presented in the principal Brief). Further, this argument is similarly not persuasive. As discussed above, the combination is using the error correcting techniques of Hwang and Nguyen in Klein and these techniques are being used for error correction; thus, the principle of operation is not changed. Appeal 2010-006811 Application 11/125,767 6 has shown that the reference teaches a dedicated cycle which results in refreshing all of the memory. Appellant’s arguments directed to the two issues have not persuaded us of error. Accordingly, we sustain the Examiner’s rejection of claims 9, 11 through 16, and 19 through 20 under 35 U.S.C. § 103(a) as unpatentable over Klein, Hwang, and Nguyen. Further, as Appellant’s arguments have presented no additional issues with respect to the rejection of clams 21 and 22, we similarly sustain the Examiner’s rejections of these claims. CONCLUSION We sustain the Examiner’s rejections of claims 9, 11 through 16, and 19 through 22 under 35 U.S.C. § 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED msc Copy with citationCopy as parenthetical citation