Ex Parte Laksono et al

Patent Trial and Appeal BoardJul 26, 2016

13076536 (P.T.A.B. Jul. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 13/076,536 03/31/2011 Indra Laksono 93253 7590 07/28/2016 Garlick & Markison (VIXS) P.O. Box 160727 Austin, TX 78716-0727 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. VIXS189US 3934 EXAMINER REN, ZHUBING ART UNIT PAPER NUMBER 2483 NOTIFICATION DATE DELIVERY MODE 07/28/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): MMurdock@texaspatents.com ghmptocor@texaspatents.com bpierotti@texaspatents.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte INDRA LAKSONO, KAI YANG, HONGRI WANG, DONG LIU, XU GANG (WILF) ZHAO, ERIC YOUNG, and EDWARD HONG 1 Appeal2015-003394 Application 13/076,536 Technology Center 2400 Before MICHAEL J. STRAUSS, DANIEL N. FISHMAN, and JAMES W. DEJMEK, Administrative Patent Judges. FISHMAN, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. Â§ 134(a) from a Final Rejection of claims 1-15. 2 We have jurisdiction over the pending claims under 35 U.S.C. Â§ 6(b ). We affirm. 1 Appellants identify VIXS Systems, Inc. as the real party in interest. Appeal Brief 2. 2 In this Decision, we refer to Appellants' Appeal Brief ("App. Br.," filed October 15, 2014); Appellants' Reply Brief ("Reply Br.," filed January 6, 2015); the Final Office Action ("Final Act.," mailed August 7, 2014 ); the Examiner's Answer ("Ans.," mailed on November 24, 2014); and the original Specification ("Spec.," filed March 31, 2011). Appeal2015-003394 Application 13/076,536 THE INVENTION Appellants' invention is directed to video decoders for stereoscopic television signals. Spec., 1: 11-12. Independent claim 9, reproduced below, is representative: 9. A method comprising: generating entropy decoded (EDC) data from an encoded video signal, wherein the EDC data includes motion vector differential data and macroblock header data and run level data; generating a decoded video signal from the EDC data via a plurality of vector processors, wherein each of the plurality of vector processors receives vector instructions including vector input data and vector command data that indicates a selected one of a plurality of functions and parallel processes the vector input data into vector output data in accordance with the vector command data, and wherein the plurality of functions include: generating motion vector data, macroblock mode data and deblock strength data, based on the motion vector differential data and the macroblock header data; generating inter-prediction data based on the motion vector data when the macroblock mode data indicates an inter-prediction mode; generating inverse quantization data based on the run level data; generating residual data, based on the inverse quantization data; generating intra-prediction data when the macroblock mode data indicates an intra-prediction mode; generating reconstructed picture data based on the residual data and on the inter-prediction data when the macroblock mode data indicates an inter-prediction mode and based on the residual data and on the intra- prediction data when the macro block mode data indicates an intra-prediction mode; and 2 Appeal2015-003394 Application 13/076,536 generating the decoded video signal from the reconstructed picture data, based on the deblock strength data. THE REJECTION Claims 1-15 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Macinnis et al. (US 2003/0185306 Al; Oct. 2, 2003) ("Macinnis") and Suk et al. (US 2011/0145549 Al; June 16, 2011 (filed Aug. 24, 2010)) ("Suk"). Final Act. 3-8. ANALYSIS Only those arguments actually made by Appellants have been considered in this Decision. Arguments that Appellants did not make in the Briefs have not been considered and are waived. See 37 C.F.R. Â§ 41.37(c)(l)(iv). We are not persuaded by Appellants' contentions of Examiner error (App. Br. 4--9; Reply Br. 2-5). We adopt as our own the findings and reasons set forth by the Examiner in the action from which this appeal is taken (Final Act. 2-8) and as set forth by the Examiner in the Answer (Ans. 2-9). However, we highlight and address specific arguments and findings for emphasis as follows. Appellants contend the Examiner erred in finding Macinnis teaches or suggests each of a plurality of vector processors receives "vector instructions including ... vector command data that indicates a selected one of a plurality of functions," as recited in claim 9. App. Br. 6-7; Reply Br. 3--4. In particular, Appellants argue the "Examiner's [A ]nswer provides no reasoning as to why a simple start command would provide more 3 Appeal2015-003394 Application 13/076,536 information that [sic] 'start', and why the start command would also indicate a selected one of each of the plurality of functions." Reply Br. 3. Appellants further argue Suk also fails to disclose the disputed limitation, and thus the combination of Macinnis and Suk is deficient. App. Br. 7-9; see also Reply Br. 3-5. We are unpersuaded the Examiner erred. The Examiner finds, and we agree, Macinnis teaches "[e]ach hardware module 306, 308, 309, 310, 312 and 314 performs its [separate individual] task after being so instructed by the core processor 302." Ans. 7-8 (citing Macinnis i-fi-129-38, 54; Figures 3 and 4). Paragraph 76 of Macinnis, relied on by the Examiner, discloses: Each hardware module 306, 308, 309, 310, 312, 313, 315 is independently controllable by the core processor 302. The core processor 302 drives a hardware module by issuing a certain start command after checking the module's status. In one embodiment, the core processor 302 issues the start command by setting up a register in the hardware module. The Examiner concludes Mac Innis's "start command from the core processor to each module may be interpreted as the vector command data ... in its broadest reasonable sense, consistent with [A ]ppellant[ s '] own disclosure." Ans. 8; see also Final Act. 4--5 (citing Macinnis i-fi-176-77). We agree. In other words, Macinnis, in disclosing a core processor issuing a certain start command to drive each hardware module, teaches or suggests each start command is individual and unique to each hardware module. We find each start command, individual and unique to each hardware module, indicates a selected one of a plurality of hardware modules. Thus, under a broad but reasonable interpretation, we agree with the Examiner in finding Macinnis teaches or suggests receiving vector instructions including a 4 Appeal2015-003394 Application 13/076,536 certain start command to drive each hardware module (the claimed "vector command data") that indicates a selected one of a plurality of hardware modules and its associated function (the claimed "functions"). For the reasons discussed supra, we are unpersuaded of Examiner error. Accordingly, we sustain the Examiner's rejection of independent claim 9 and, for similar reasons, the rejection of independent claim 1, which contains similar limitations and is argued together with claim 9. App. Br. 9. Additionally, we sustain the Examiner's rejections of dependent claims 2-8 and 10-15, which are not argued separately with particularity. Id. DECISION We affirm the Examiner's decision to reject claims 1-15 under 35 U.S.C. Â§ 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 3 7 C.F .R. Â§ 1.13 6( a)( 1 )(iv). AFFIRMED 5