Ex Parte Kwark

Patent Trial and Appeal Board

Sep 29, 2014

11411920 (P.T.A.B. Sep. 29, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/411,920 04/27/2006 Young Hoon Kwark YOR920050592US1 7476
48150 7590 09/29/2014
MCGINN INTELLECTUAL PROPERTY LAW GROUP, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA, VA 22182-3817
EXAMINER
MIYOSHI, JESSE Y
ART UNIT PAPER NUMBER
2896
MAIL DATE DELIVERY MODE
09/29/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte YOUNG HOON KWARK
____________

Appeal 2012-007335
Application 11/411,9201
Technology Center 2800
____________

Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.

HOUSEL, Administrative Patent Judge.

DECISION ON APPEAL

Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
decision finally rejecting claims 1–4, 6, 7, and 21–34. We have jurisdiction
over the appeal under 35 U.S.C. § 6(b).
We AFFIRM.2

1 According to Appellant, the Real Party in Interest is International Business
Machines Corporation (Appeal Br. 1).
2 Our decision refers to Appellant’s Brief (Appeal Br.) filed October 11,
2011, the Examiner’s Answer (Answer) mailed February 3, 2012, and
Appellant’s Reply Brief (Reply Br.) filed on April 3, 2012.
Appeal 2012-007335
Application 11/411,920

2
STATEMENT OF THE CASE
The invention is directed to integrated circuit chip packaging
connecting an integrated circuit chip to a conductive layer (conductor)
embedded between layers of a printed circuit board. Spec. 1:10–13.
Appellant discloses that a cavity in the printed circuit board receives the
integrated circuit chip with an electrical connection to connect to the chip to
the embedded conductor. Id. at 2:7–16. Moreover, the printed circuit board
may include a plurality of insulating layers, and alternating stacks of
patterned conductors embedded between the layers, wherein the cavity
extends from the surface of the printed circuit board to the embedded
conductors. Id. at 4:1–3, 4:8–15. According to Appellant, the cavity allows
more direct access to a conductor, without having to rely on a surface mount
or a via to connect to an embedded conductor. Id. at 4:4–7.
Claim 1, reproduced below, is representative of the subject matter on
appeal:
1. An electrical circuit device, comprising:
a printed circuit board with a cavity extending from a top
surface of said printed circuit board to a top surface of an
embedded conductor, said printed circuit board contacting an
upper surface and a lower surface of said embedded conductor
inside the printed circuit board;
an integrated circuit chip that is disposed on a lower
surface of said cavity inside the printed circuit board such that
said printed circuit board extends below the integrated circuit
chip and covers a side surface of the integrated circuit chip; and
an electrical connection between said integrated circuit
chip and said embedded conductor.
Claims App’x, Appeal Br. 19.
Appeal 2012-007335
Application 11/411,920

3
The Rejections
The Examiner maintains the following rejections:3
1) Rejection of claims 21, 23, 26, and 27–34 under 35 U.S.C.
§ 112, first paragraph, as failing to comply with the written
description requirement;4

2) Rejection of claims 6, 7, 26, 28, and 33 under 35 U.S.C.
§ 112, second paragraph, as being indefinite for failing to
particularly point out and distinctly claim the subject matter
which applicant regards as the invention;5

3 The Examiner does not repeat all of the rejections maintained from the
Final Rejection of May 11, 2011 in the Answer, but instead indicates that
every ground of rejection set forth therein is maintained unless expressly
withdrawn. Answer 4. Because all of the rejections are maintained, we
reproduce them all here.
4 The Examiner’s statement of this rejection omits claims 27 and 28, yet
claim 27 is discussed in the body of this rejection. See Answer 6. While
Appellant does not discuss claim 27, we note the limitation the Examiner
discusses in this claim is the same as that of claims 23 and 31, claims that
Appellant does address in the Appeal Brief. Answer 6 and Appeal Br. 10.
In fact, the Examiner’s position against claim 27 as presented in the Answer
is identical to that set forth in the Final Rejection mailed May 11, 2011. In
addition, claim 28 also contains the same limitation in question by virtue of
its dependency from claim 27. Accordingly, we hold the omission of claims
27 and 28 from this rejection statement to be harmless error.
5 The Examiner sets forth this rejection as applying to claims 6, 7, and 21–
25. However, in the body of the rejection, the Examiner discusses claims 6,
26, 28, and 33, without any mention of claims 21–25 (claim 7 is presumably
included by virtue of its dependence on claim 6). Unfortunately, the
Examiner’s statement of rejection is not the model of clarity as to which
claims the Examiner considers to lack compliance with this statutory
requirement, nor does Appellant make any attempt to question or clarify
which claims are subject to this rejection. In fact, Appellant argues against
an indefiniteness rejection applied to claims 6, 26, and 33 only (omitting any
mention of claim 28). Given the body of the rejection refers to claims 6, 26,
28, and 33 only, without any reference to claims 21–25, we have modified
Appeal 2012-007335
Application 11/411,920

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3) Rejection of claims 1–4, 23, 27, and 28 under 35 U.S.C.
§ 102(b) as anticipated by Shirakawa (US 5,831,833, issued
November 3, 1998);

4) Rejection of claim 29 and 31 under 35 U.S.C. § 103(a) as
being unpatentable over Shirakawa;

5) Rejection of claim 22 under 35 U.S.C. § 103(a) as being
unpatentable over Shirakawa in view of Lin (US 5,508,556,
issued April 16, 1996);

6) Rejection of claims 24 and 25 under 35 U.S.C. § 103(a) as
being unpatentable over Shirakawa in view of Newman (US
5,490,324, issued February 13, 1996);

7) Rejection of claim 6 under 35 U.S.C. § 103(a) as being
unpatentable over Shirakawa in view of Marcantonio (US
5,796,170, issued August 18, 1998);

8) Rejection of claim 7 under 35 U.S.C. § 103(a) as being
unpatentable over Shirakawa in view of Marcantonio and
Huang (US 6,469,592 B2, issued October 22, 2002);

9) Rejection of claim 21 under 35 U.S.C. § 103(a) as being
unpatentable over Shirakawa in view of Huang, Beutel (US
6,428,908 B1, issued August 6, 2002), and Newman;

10) Rejection of claim 26, 30, 32, and 34 under 35 U.S.C.
§ 103(a) as being unpatentable over Shirakawa in view of
Newman and Huang; and

11) Rejection of claim 33 under 35 U.S.C. § 103(a) as being
unpatentable over Shirakawa in view of Newman, Lin, and
Huang.

the Examiner’s statement accordingly, presuming that claims dependent on
these claims were intended to be included.
Appeal 2012-007335
Application 11/411,920

5
Appellants do not request review of Rejections 3, and 7–11 above.
See Appeal Br. 9. We note that Appellant erroneously requests review of a
Section 103 rejection of claims 2 and 27. See Appeal Br. 9, 13; Reply Br. 5.
Claims 2 and 27 are subject to rejection under Section 102(b), and not
Section 103. See Answer 8. Nonetheless, we have considered Appellant’s
arguments for claims 2 and 27 as applying to the Section 102(b) rejection of
these claims at the end of this decision. Accordingly, we summarily affirm
Rejection 3 as to claims 1, 3, 4, and 23 (claim 28 depends from claim 27),
and Rejections 7–11.
In addition, Appellant does not request review of Rejection 2 as
applied to claim 28. See id. at 9, 12; Reply Br. 4–5. Accordingly, we
summarily affirm Rejection 2 as applied to claim 28.
To the extent that the claims on appeal are separately argued, we will
address them separately consistent with 37 C.F.R. § 41.37(c)(1)(vii).

ANALYSIS
Rejection 1: 35 U.S.C. § 112, first paragraph
We note the Examiner references a limitation at line 10 of claim 33,
“a ribbon bond and a ball bond electrically connects said integrated circuit
chip with said ground plane.” Answer 6, item 11. As Appellant correctly
notes, claim 33 does not recite such a limitation, but instead recites “‘a
ribbon bond rather than a ball bond electrically connects said integrated
circuit chip with said ground plane.’” Appeal Br. 11. The Examiner does
not respond to Appellant’s point. Therefore, we will not sustain this aspect
of the Examiner’s rejection.
Claim 21
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6
The Examiner finds the original disclosure fails to support the
limitation, “‘each of said plurality of connections comprises a ball bond and
a ribbon bond,’” as set forth in this claim. Answer 5. Appellant disputes
this finding, arguing that at least as shown in Figure 2 and related text in the
Specification, “each of the plurality of connections 218 includes a ball bond
and a ribbon bond.” Appeal Br. 11; Reply Br. 2–3. In response, the
Examiner notes in reference to Appellant’s Figure 2 and Specification
paragraphs [0046] and [0047] (from the published application) that there is
no support for both a ball bond and a ribbon bond in any single connection
between the integrated circuit chip and an embedded conductor. Answer
18–19.
We are not persuaded of reversible error in the Examiner’s finding as
to lack of support for the limitation in question. Original Figure 2
specifically distinguishes between ribbon bonds 210 and ball bonds 218,
without indicating that any of these bonds are both ribbon and ball bonds,
simultaneously. Although, as noted by the Examiner, the third of these five
bonds was changed from a ribbon bond to a ball bond in Appellant’s
amended Figure 2, Appellant never indicated that any one connection was
both a ribbon and ball bond. Finally, the Specification describes each
connection depicted in Figure 2 as either a ribbon bond 210 or a ball bond
218, but not both. Spec. 9:18–20 (“The top of the chip 204 may be
connected to the highest performance embedded conductor 208 with a
ribbon bond 210 because a ribbon bond may offer a higher performance
potential.”); 10:17–18 (“Further, the next closest embedded conductors 216
to the top of the chip 204 are connected by ball bonds 218 to the chip 206.”)
Appellant fails to direct our attention to any express, implicit, or inherent
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disclosure in support of any electrical connection between the chip and an
embedded conductor that is both a ribbon bond and a ball bond, nor do we
find any. We, therefore, will sustain the rejection of this claim for lack of
written descriptive support.
Claims 23, 27, and 31
The Examiner finds the original disclosure fails to support the
limitation, “said printed circuit board comprises a single layer” in claim 23,
“said printed circuit board is single layer” in claim 27, and “a single layer
printed circuit board” in claim 31. Answer 5, 6. Appellant disputes this
finding, arguing that Figure 2 shows a single layer printed circuit board 200.
Appeal Br. 10; Reply Br. 1–2. Appellant further argues that one of ordinary
skill in the art would have considered milling the cavity as being performed
on a single layer board. Id. In response, the Examiner notes that
Appellant’s original disclosure not only failed to teach a single layer printed
circuit board, but in fact specifically teaches the printed circuit board is
multi-layered. Answer 15.
We are not persuaded of reversible error in the Examiner’s finding as
to lack of support for the limitation in question. Original Figure 2 is at best
ambivalent as to whether the printed circuit board is single or multi-layered.
However, we agree with the Examiner that Appellant’s Specification clearly
teaches that the printed circuit board having an embedded conductor is
multi-layered. See, for example, Spec. 1:11–13 (“More particularly, the
present invention relates to integrated circuit chip packaging connecting an
integrated circuit chip to a conductive layer embedded between layers of a
printed circuit board.”) Such disclosures of multiple layers of the printed
circuit board occur throughout the Specification. Appellant fails to direct
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Application 11/411,920

8
our attention to any express, implicit, or inherent disclosure in support of a
single layer printed circuit board, nor do we find any. We, therefore, will
sustain the rejection of these claims for lack of written descriptive support.
Claims 26, 30, 33, and 34
The Examiner finds the original disclosure fails to support the
limitation, “a ribbon bond and a ball bond electrically connects said
integrated circuit chip with said another embedded conductor,” as recited in
each of these claims. Answer 6, 7. This limitation is substantially the same
as that in claim 21, requiring both a ribbon bond and a ball bond for a single
connection. Indeed, Appellant’s arguments as to these claims mirror those
against the written description rejection of claim 21. Accordingly, for the
same reasons given above for claim 21, we will sustain the rejection of these
claims for lack of written descriptive support.
Claims 29 and 31
The Examiner finds the original disclosure fails to support the
limitation, “a side surface of said printed circuit board abuts the side surface
of the integrated circuit chip,” as set forth in claim 29 and the similar
limitation of claim 31. Answer 6. Appellant disputes this finding, arguing
that Figure 2 and related text in the Specification shows and describes “a
side surface of the printed circuit board 200 abuts the side surface of the
integrated circuit chip 204, which is embedded in the printed circuit board
200.” Appeal Br. 11. In response, the Examiner notes, “as can be seen in
the originally filed Figure 2, there is a space provided between the side
surface of the printed circuit board and the side surface of the integrated
circuit chip.” Answer 19.
Appeal 2012-007335
Application 11/411,920

9
We are not persuaded of reversible error in the Examiner’s finding as
to lack of support for the limitation in question. Appellant’s original Figure
2 is again at best ambivalent as to whether the side surfaces of the integrated
circuit chip and printed circuit board cavity abut. However, we agree with
the Examiner that Appellant’s Specification does not expressly, implicitly,
or inherently teach that these two structures do in fact abut, rather than have
a small gap therebetween. Further, Appellant fails to direct our attention to
any textual description that reasonably supports the limitation in question,
nor do we find any.
“[U]nder proper circumstances, drawings alone may provide a
‘written description’ of an invention as required by § 112.” Vas-Cath Inc. v.
Mahurkar, 935 F.2d 1555, 1565 (Fed. Cir. 1991). The proper test is whether
the drawings convey with reasonable clarity to those of ordinary skill in the
art that Appellants had in fact invented (were in possession of) the subject
matter as recited in the claims. Id. at 1566. Importantly, the feature in
question here is not particularly clear in original Figure 2 and, as the
Examiner finds, does appear to show a small gap between the side surface of
the printed circuit board cavity and the side surface of the integrated circuit
chip. Appellant has not evinced that original Figure 2 conveys with
reasonable clarity to the ordinary artisan that Appellant has in fact invented
the integrated circuit package as recited in these claims. We, therefore, will
sustain the rejection of these claims for lack of written descriptive support.

Appeal 2012-007335
Application 11/411,920

10
Rejection 2: 35 U.S.C. § 112, second paragraph
Claim 6
The Examiner finds the recitation, “‘a plurality of embedded
conductors, which are embedded within the printed circuit board in addition
to the embedded conductor’” to be indefinite because it is unclear as to
which element “the embedded conductor” is referring. Answer 7. Appellant
argues that the embedded conductor refers to the embedded conductor of
claim 1. Appeal Br. 12. Appellant notes Figure 2 shows a plurality of
embedded conductors 216 in addition to embedded conductor 208. Id. As
such, Appellant asserts claim 6 is definite.
We agree. Although the Examiner urges that it is unclear which
instance of embedded conductor the further statement in claim 6 refers, the
clause beginning “which are embedded within the printed circuit board”
clearly refers back to and modifies the plurality of embedded conductors
immediately preceding this clause in the claim. Therefore, the ordinary
artisan would have no difficulty recognizing that the “in addition to the
embedded conductor” refers to the embedded conductor previously recited
in independent claim 1. We, therefore, will not sustain the indefiniteness
rejection of claim 6.
Claims 26 and 33
The Examiner finds the recitation, “‘a ribbon bond rather than a ball
bond’” to be indefinite because it is unclear whether the elements are the
same or different from each other. Answer 7. Appellant argues that one of
ordinary skill in the art would have understood that a ribbon bond
electrically connects the integrated circuit chip with the ground plane.
Appeal Br. 12. Appellant notes Figure 2 shows a ribbon bond 210 rather
Appeal 2012-007335
Application 11/411,920

11
than a ball bond 218 electrically connects the integrated circuit chip 204
with the ground plane 214. Id. As such, Appellant asserts claims 26 and 33
are definite.
We agree. Although the Examiner urges that “a ribbon bond rather
than a ball bond” implies that first a ball bond is made, then removed and
replaced by a ribbon bond, Appellant correctly submits that this phrase
merely excludes a particular connection, i.e., ball bond, while positively
reciting a particular connection, i.e., ribbon bond. Reply Br. 5. Therefore,
the ordinary artisan would have no difficulty recognizing that the claim
requires a ribbon bond connection between the integrated circuit chip and
the ground plane, while excluding a ball bond connection therebetween.
We, therefore, will not sustain the indefiniteness rejection of claims 26 and
33.

Rejection 3: 35 U.S.C. § 102(b) rejection
Claim 2
Appellant argues Shirakawa fails to teach or suggest “the top surface
of said integrated circuit chip is substantially co-planar with a top surface of
the embedded conductor.” Appeal Br. 15. In support of this argument,
Appellant contends that Shirakawa, Figure 4B clearly shows the top surface
of the integrated circuit chip 1 is placed substantially higher than the top
surface of the conductor layer 12. Id. However, Appellant mischaracterizes
the Shirakawa reference as applied by the Examiner in the rejection. The
Examiner finds Figure 6, not Figure 4B, anticipates Appellant’s claimed
invention. Answer 8, 9. We find no error in the Examiner’s finding, relative
to Shirakawa, Figure 6, that the top surface of chip 1 is substantially co-
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Application 11/411,920

12
planar with the top surface of conductor layer 12. As such, we will sustain
the Examiner’s anticipation rejection of claim 2.
Claim 27
The Examiner finds “Shirakawa teaches the device, wherein said
printed circuit board (10) is [a] single layer.” Answer 8. The Examiner
further finds that “if Appellant’s multilayered printed circuit board is
considered ‘a single layer printed circuit board’, clearly Shirakawa's
multilayered printed circuit board is considered ‘a single layer printed circuit
board’.” Answer 22. Appellant argues that not only has the Examiner failed
to show Shirakawa teaches or suggests this feature, Shirakawa in fact
teaches a multilayered board 10, including layer 12 sandwiched between
upper and lower layers 11. Appeal Br. 13.
We are persuaded the Examiner’s finding that Shirakawa teaches a
single layer printed circuit board is reversible error. The Examiner fails to
direct our attention to any disclosure in Shirakawa that the printed circuit
board is, or could be, a single layer structure. As Appellant argues,
Shirakawa teaches a multi-layered printed circuit board having a conductive
layer 12 embedded between layers 11. See, for example, Shirakawa, Fig. 6.
As such, we will not sustain the Examiner’s anticipation rejection of claim
27. Because claim 28 depends from claim 27, we further do not sustain the
rejection of claim 28.

Rejection 4: 35 U.S.C. § 103(a) rejections
Claims 29 and 31
As to claim 31, Appellant argues Shirakawa fails to teach a single
layer printed circuit board. Although the Examiner rejected claim 31 under
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Section 103 as being unpatentable over Shirakawa, the Examiner relies on
the prior findings that Shirakawa teaches a single layer printed circuit board,
at least to the extent that Appellant does so. For the same reasons given
above, we are persuaded of reversible error in the Examiner’s Section 103
rejection of claim 31.
As to claim 29, the Examiner finds
[i]t is known in the semiconductor fabrication industry that
reducing the amount of wiring within a device will reduce
resistance and parasitic capacitances, therefore, it is a
motivation when producing semiconductor devices to reduce
wiring.

Answer 12. Therefore, the Examiner concludes it would have been obvious
to lessen the amount of wiring by abutting the chip to the embedded
conductor in Shirakawa in order to reduce resistance and parasitic
capacitances. Id.
Appellant disputes the Examiner’s finding as to what was known in
the industry, arguing the Examiner has not provided any evidence in support
that this finding was well known in the industry, let alone in the environment
of the claimed invention. Appeal Br. 14; Reply Br. 8. In response, the
Examiner refers to Moore’s law, describing the relationship between
resistivity and the length of a conductor. Answer 22–23. However, the
Examiner fails to provide any evidentiary support for the application of
Moore’s law to the wiring in Shirakawa. Indeed, in each and every
embodiment disclosed in Shirakawa, a space is provided on both sides of the
integrated circuit chip. Accordingly, we are persuaded of reversible error in
the Examiner’s rejection of claim 29 over Shirakawa.

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Claims 24 and 25
The Examiner finds Shirakawa teaches a known layout of an arbitrary
number of layers stacked in a printed circuit board, with the recess shaped
by removing insulating layers 11 to expose conductors 12. Answer 10. The
Examiner further finds Newman teaches a ground plane (442) embedded
within the printed circuit board above an embedded conductor (438),
wherein the printed circuit board contacts (abuts) a lower surface and an
upper surface of said ground plane (442) inside the printed circuit board. Id.
The Examiner determines it would have been obvious to have provided
Shirakawa with a ground plane above the embedded conductor 12 inside the
printed circuit board, similarly to the embedded conductor 12 such that the
board abuts a lower surface and an upper surface of the ground plane as
taught in Newman. Id.
Appellant argues that Newman fails to teach that the printed circuit
board abuts an upper and a lower surface of a ground plane inside the
printed circuit board as recited in these claims. Appeal Br. 16. Appellant
contends Newman teaches “the lower surface of the conductive layer 442
abuts PWB 404, whereas the upper surface of the conductive layer 442 abuts
adhesive layer 418 (Fig. 4a).” Reply Br. 9.
However, Appellant mischaracterizes Newman’s teaching. Newman
teaches the ground plane is inside the printed circuit board. See Newman,
1:58–67 (“the PGA or BGA package is a miniature multi-layer printed
circuit board system.”) Moreover, Appellant has not addressed the
Examiner’s reasoning that it would have been obvious in view of Newman’s
multi-layered structure to have provided a similarly embedded ground plane
conductor within the layers of Shirakawa’s printed circuit board.
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Accordingly, Appellant has not shown reversible error in the combination of
Shirakawa and Newman as proposed by the Examiner.
Claim 22
The Examiner finds Shirakawa teaches the structure as claimed except
for a ground plane within the printed circuit board to abut a lower surface of
the integrated circuit chip. Answer 9. However, the Examiner finds Lin
teaches that mounting an integrated circuit chip onto a ground plane
significantly reduces the number of leads or electrical connections needed to
connect the chip. Id. The Examiner concludes it would have been obvious
to provide that one of the plurality of embedded conductors is a ground
plane upon which the integrated circuit chip is mounted to reduce the wiring
needed for the chip as taught by Lin. Id. at 9–10.
Appellant argues that Lin fails to teach or suggest a ground plane
embedded within a printed circuit board to abut a lower surface of the
integrated circuit chip, the printed circuit board abutting a lower surface and
an upper surface of the ground plane inside the printed circuit board. Appeal
Br. 16–17. However, Appellant fails to address the Examiner’s specific and
contrary finding that Lin teaches the claimed feature in a manner such that
the ordinary artisan would have found it obvious to do so in Shirakawa in
order to reduce the wiring required for the chip. As such, we are not
persuaded of reversible error in the Examiner’s proposed combination of
Shirakawa and Lin.

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ORDER
Upon consideration of the record, and for the reasons given above, it
is
ORDERED that the decision of the Examiner rejecting claims 21, 23,
26, 27, and 29–34 under 35 U.S.C. § 112, first paragraph, is affirmed;
ORDERED that the decision of the Examiner rejecting claim 28 under
35 U.S.C. § 112, second paragraph, is affirmed;
ORDERED that the decision of the Examiner rejecting claims 6, 7,
and 33 under 35 U.S.C. § 112, second paragraph, is reversed;
ORDERED that the decision of the Examiner rejecting claims 1–4
and 28 under 35 U.S.C. § 102(b) as anticipated by Shirakawa is affirmed;
ORDERED that the decision of the Examiner rejecting claims 23, 27
and 28 under 35 U.S.C. § 102(b) as anticipated by Shirakawa is reversed;
ORDERED that the decision of the Examiner rejecting claim 6 under
35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view of
Marcantonio is affirmed;
ORDERED that the decision of the Examiner rejecting claim 7 under
35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view of
Marcantonio and Huang is affirmed;
ORDERED that the decision of the Examiner rejecting claim 21 under
35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view of Huang,
Beutel, and Newman is affirmed;
ORDERED that the decision of the Examiner rejecting claims 29 and
31 under 35 U.S.C. § 103(a) as being unpatentable over Shirakawa is
reversed;
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ORDERED that the decision of the Examiner rejecting claim 22 under
35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view of Lin is
affirmed;
ORDERED that the decision of the Examiner rejecting claims 24 and
25 under 35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view
of Newman is affirmed;
ORDERED that the decision of the Examiner rejecting claims 26, 30,
32, and 34 under 35 U.S.C. § 103(a) as being unpatentable over Shirakawa
in view of Huang and Newman is affirmed;
ORDERED that the decision of the Examiner rejecting claim 33 under
35 U.S.C. § 103(a) as being unpatentable over Shirakawa in view of
Newman, Lin, and Huang is affirmed; and
FURTHER ORDERED that no time period for taking any subsequent
action in connection with this appeal may be extended under 37 C.F.R.
§ 1.136(a)(1).

AFFIRMED

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