Ex Parte Kuzmin et alDownload PDFPatent Trial and Appeal BoardMay 31, 201714466167 (P.T.A.B. May. 31, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/466,167 08/22/2014 Andrey V. Kuzmin 2014058 / RMS-02C1 5586 73091 7590 Marc P. Schuyler P.O. Box 2535 Saratoga, CA 95070 05/31/2017 EXAMINER BIRKHIMER, CHRISTOPHER D ART UNIT PAPER NUMBER 2136 MAIL DATE DELIVERY MODE 05/31/2017 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ANDREY V. KUZMIN, MIKE JADON, and RICHARD M. MATHEWS Appeal 2017-001221 Application 14/466,167 Technology Center 2100 Before CARLA M. KRIVAK, IRVIN E. BRANCH, and KARA L. SZPONDOWSKI, Administrative Patent Judges. SZPONDOWSKI, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 16—21 and 23—26. Claims 1—15 and 22 have been cancelled. App. Br. 19, 21. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. Appeal 2017-001221 Application 14/466,167 STATEMENT OF THE CASE Appellants’ invention is directed to cooperative interaction between a memory controller and a host, and in particular to a memory controller that provides addresses to host. Spec. Title, 133. Claim 16, reproduced below with the disputed limitations in italics, is illustrative of the claimed subject matter: 16. A memory controller integrated circuit for flash memory, the memory controller integrated circuit to store and retrieve data at locations in the flash memory responsive to host commands, the memory controller integrated circuit comprising: storage for entries, each entry representing status of a page in the flash memory capable of storing data pursuant to the host commands, all pages capable of storing data pursuant to the host commands having a corresponding entry regardless of the values of data stored in a given one of the pages; logic to update the entries responsive to changes in status of corresponding pages in the flash memory; logic to receive a query from the host which seeks identification of one or more of the locations in the flash memory that satisfy at least one condition from the set of (a) data stored at the corresponding location satisfies a data age requirement, (b) data stored at the corresponding location satisfies an access frequency requirement, (c) a requisite number of physical pages at the corresponding location have been released but are in an unerased condition, or (d) all physical pages corresponding to the location have been released but are in an unerased condition; logic to detect, responsive to the query, when the entries indicate that one or more of the locations in the flash memory satisfy the at least one condition; and logic to, responsive to detection that the one or more locations satisfy the at least one condition, to [sic] transmit address information 2 Appeal 2017-001221 Application 14/466,167 to the host corresponding to the one or more locations for which the at least one condition is satisfied; and logic to receive from the host a maintenance command dependent on the address information transmitted to the host and to process the received maintenance command, wherein the maintenance command is to cause said memory controller integrated circuit to perform at least one of (i) relocation of a page within the one or more locations to a different erase block in the flash memory or (ii) erasure of an erase block corresponding to the one or more locations, and wherein the maintenance command is to specify an address of each page or erase block within the one or more locations that is to be the subject of the at least one of relocation or erasure pursuant to the maintenance command. REJECTIONS1 Claims 16—21 and 23—26 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Spencer (US 2003/0065866 Al; published Apr. 3, 2003) and Allen et al. (US 2009/0172250 Al; published July 2, 2009) (hereinafter “Allen”). ANALYSIS Dispositive Issue'. Did the Examiner err in finding the combination of Spencer and Allen teaches or suggests “logic to, responsive to detection that the one or more locations satisfy the at least one condition, to transmit address information to the host corresponding to the one or more locations for which the at least one condition is satisfied,” as recited in independent claim 16? 1 In the Answer, the Examiner withdrew the rejections of claims 16—21 and 23—26 under 35 U.S.C. § 101 and the rejection of claim 20 under 35 U.S.C. § 112(b). Ans. 2-3. 3 Appeal 2017-001221 Application 14/466,167 Appellants argue “[t]here is no disclosure that any type of address information (as claimed by Applicant) is provided by Spencer’s memory controller to his host.” App. Br. 10. Appellants argue “address information (e.g., sector/cluster location information) is NOT PROVIDED to the host and is exclusively maintained by the memory controller.” App. Br. 10 (citing Spencer || 50, 51). We are persuaded by Appellants’ arguments. The Examiner relies on paragraphs 42 and 49 of Spencer to teach or suggest the disputed limitation. Ans. 3^4. Paragraph 42 describes in part: TTlhe memory card controller 130 outputs to the host device 100 information concerning the available sectors or clusters on the memory card 120, and the host device 100 outputs data to the memory card controller 130 to fill up each of those available sectors or clusters on the memory card 120, until the file is fully written onto the memory card 120. Spencer 142 (emphasis added). Paragraph 49 states: In the second embodiment, the memory card controller 130 indicates the available storage locations and sizes to the host device 100, and the host device 100 would act on that information to then transfer sectors of data for the file to the memory card 120, by way of the memory card controller 130. The host device 100 is not provided with the entire FAT, but just with the necessary information so that it can send the appropriate sectors of data consecutively to the memory card 120 (e.g., host device 100 sends the entire file, e.g., 150 sectors for a 75 kByte file, as a continuous data stream, to the memory card, whereby the memory card controller would take care of writing the file into the appropriate, available clusters of the memory card.). Spencer 149 (emphasis added). 4 Appeal 2017-001221 Application 14/466,167 Appellants direct our attention (App. Br. 10) to paragraph 51 of Spencer, which also describes the second embodiment. Paragraph 51 states: In the second embodiment, all of the FAT management and FAT updating is done by the memory card controller 130, and thus the host device 100 only has to output the data file to be written to the memory card 120, and the host device 100 is not provided with any FAT information as to the memory locations (e.g., sectors or clusters) of the memory card 120 on which the data file is being written to by the memory card controller 130. The memory card controller 130 exclusively maintains that information. Spencer | 51 (emphasis added). The Examiner does not address paragraph 51 in the Answer. Having considered the Examiner’s findings with respect to the teachings in Spencer, we find the Examiner has failed to provide sufficient findings that show that Spencer teaches or suggests the disputed limitation. Specifically, we do not find “indicating] the available storage locations and sizes” or “information concerning the available sectors or clusters on the memory card” teaches transmitting address information, as the claim requires. Rather, the host device in Spencer is only provided with the necessary information so it can send appropriate sectors of data. Spencer Tflf 49, 50. Moreover, Spencer explicitly states that the memory controller exclusively maintains the FAT information as to the memory locations. Spencer | 51. In addition, we observe the claim further recites “logic to receive from the host a maintenance command dependent on the address information transmitted to the host. . . and wherein the maintenance command is to specify an address.” Again, the Examiner relies on Spencer. Final Act. 6—7 (citing Spencer 100, Fig. 1; 320, 330, Fig. 4; 420, 430, Fig. 5, Tflf 15, 17, 42). 5 Appeal 2017-001221 Application 14/466,167 However, we do not discern from the citations provided by the Examiner where the access commands issued in Spencer specify an address. Because we agree with at least one of the arguments advanced by Appellants, we need not reach the merits of Appellants’ other arguments. Accordingly, we do not sustain the Examiner’s 35 U.S.C. § 103(a) rejection of independent claim 16. For the same reasons, we do not sustain the Examiner’s 35 U.S.C. § 103(a) rejection of dependent claims 17—21 and 23— 26. DECISION For the above reasons, the Examiner’s rejection of claims 16—21 and 23—26 is reversed. REVERSED 6 Copy with citationCopy as parenthetical citation