Ex Parte Kuzmin et al

Patent Trial and Appeal Board

Mar 14, 2017

13767723 (P.T.A.B. Mar. 14, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/767,723 02/14/2013 Andrey V. Kuzmin 2013007/RMS-02 8863
73091 7590
Marc P. Schuyler
P.O. Box 2535
Saratoga, CA 95070
EXAMINER
BIRKHIMER, CHRISTOPHER D
ART UNIT PAPER NUMBER
2136
MAIL DATE DELIVERY MODE
03/14/2017 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RADIAN MEMORY SYSTEMS, LLC1
Appeal 2015-008137
Application 13/767,723
Technology Center 2100
Before CARLA M. KRIVAK, IRVIN E. BRANCH, and
KARA L. SZPONDOWSKI, Administrative Patent Judges.
SZPONDOWSKI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—3, 5, 7—30, and 32—39, constituting all the claims
pending in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 Andrey V. Kuzmin, Mike Jadon, and Richard M. Mathews are named as
inventors.
Appeal 2015-008137
Application 13/767,723
STATEMENT OF THE CASE
Appellant’s invention is directed to a cooperative flash memory
controller, and specifically to the architecture of storage systems that utilize
flash memory. Spec. H 1, 2. Claim 1, reproduced below with the disputed
limitations in italics, is illustrative of the claimed subject matter:
1. A memory controller to interact with a memory having at
least one memory array, the at least one memory array having
physical storage locations, the memory controller comprising:
at least one interface to receive memory commands from
a host and to exchange data in association with the
memory commands between a host and the at least
one memory array;
logic operable to store in a management table
information for every physical storage location of
the at least one memory array, the information for
each physical storage location representing at least
one of operability of memory cells within the
physical storage location, wear of memory cells
within the physical storage location, period since
last programming of valid data within the physical
storage location, or validity status of any data
stored within the physical storage location; and
logic operable to send to a host information regarding at
least one of the physical storage locations of the at
least one memory array in dependence on the
information retained in the management table;
where the information to be sent to the host by the logic
operable to send includes at least one of
state of the at least one of the physical storage
locations of the at least one memory array,
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Application 13/767,723
wherein the state is not data values stored in
the at least one memory array, or
an identification of one or more addresses
corresponding to at least one of the physical
storage locations that match a particular
state condition.
REJECTIONS
Claims 1-3, 5, 7-8, 11, 15-17, 19, 22, 23, 25-27, 29, 30, 33, and 36
stand rejected under 35 U.S.C. § 103(a) as being unpatentable over the
combination of Ito et al. (US 8,065,473 B2; issued Nov. 22, 2011) (“Ito”)
and Yano et al. (US 7,962,688 B2; issued June 4, 2011) (“Yano”).
Claim 9 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and Asynchronous,
Webopedia (“Webopedia”).
Claim 10 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, Webopedia, and Gillingham
et al. (US 2010/0115172 Al; published May 6, 2010) (“Gillingham”).
Claim 12 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and William Wong, Expect
More Mixed Cores, Less Power, And Faster Storage, Electronic Design
(Dec. 19, 2011) (“Wong”).
Claim 13 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and Chow et al. (US
2008/0147964 Al; published June 19, 2008) (“Chow”).
Claims 14, 18, 34, 35, and 37—39 stand rejected under 35 U.S.C.
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Application 13/767,723
§ 103(a) as being unpatentable over the combination of Ito, Yano, and
Maeda et al. (US 2006/0221719 Al; published Oct. 5, 2006) (“Maeda”).
Claim 20 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and Cornwell et al. (US
7,861,122 B2; issued Dec. 28, 2010) (“Cornwell”).
Claim 21 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and Kimbrell (US
2009/0036163 Al; published Feb. 5, 2009) (“Kimbrell”).
Claim 24 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and SiliconFarEast.com
(System on a Chip (SOC), 2005).
Claim 28 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, Maeda, and Jennings III
(US 6,134,631; issued Oct. 17, 2000) (“Jennings”).
Claim 32 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Ito, Yano, and Jou et al. (US
5,568,423; issued Oct. 22, 1996) (“Jou”).
ANALYSIS
Dispositive Issue: Did the examiner err in finding the combination of
Ito and Yano teaches or suggests
logic operable to send to a host information regarding at
least one of the physical storage locations of the at least one
memory array in dependence on the information retained in the
management table;
where the information to be sent to the host by the logic
operable to send includes at least one of
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Appeal 2015-008137
Application 13/767,723
state of the at least one of the physical storage locations
of the at least one memory array, wherein the state is not data
values stored in the at least one memory array, or
an identification of one or more addresses corresponding
to at least one of the physical storage locations that match a
particular state condition,
as recited in independent claim 1 and commensurately recited in
independent claims 22, 23, 29, and 37?
Appellant contends
Ito nowhere says that physical address information, or state of
physical address locations is ever provided to the host, or that
information regarding specific physical addresses for such
locations (whether or not data appears there) is maintained by
the memory controller, or that information derived from a
management table as claimed is ever provided to a host.
App. Br. 16. Appellant further contends
Ito’s partition information . . . does not correspond to the
limitations of Applicant’s claims; that is, Ito’s partition
information identifies boot flag, start sector (of where user data
is written), file system format, and partition area information —
this information may convey information about the
interpretation of data stored in select locations of Ito’s memory
card, but it is NOT state of the physical locations themselves.
Reply Br. 5.
We are persuaded by Appellant’s arguments. The Examiner relies on
Ito to teach all of the disputed limitations except for the claimed
management table, for which the Examiner relies on Yano. Final Act. 4—6.
We have reviewed the citations relied upon by the Examiner (Final Act. 4—5,
citing Ito Fig. 2, col. 3,11. 62—67, col. 4,11. 30-67, col. 6,11. 9-21, col. 7,11.
52-58, col. 9,11. 31-38,11. 55-67, col. 14,11. 8-12, 63-67), and find the
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Examiner has failed to provide sufficient findings to show that the
combination of Ito and Yano teaches or suggests the disputed limitation, and
specifically, that Ito teaches or suggests the controller comprises logic
operable to send to the host the claimed state information.
The Examiner finds “[t]he host uses the management information to
identity certain flag values in memory and also start positions when
requested. For the host to be able to identity these certain areas of memory
it shows the information [is] sent to the host.” Ans. 7, citing Ito col. 9,11.
55—67, col. 5,11. 1^4; see also Final Act. 5 (“[t]he start position and flag
values are state information about the memory locations.”). The Examiner
further finds “Ito positively teaches that the management information is
analyzed by the host showing the host does receive the information. The
process of the host receiving information and analyzing the information
shows the use of supporting logic to allow the process to occur.” Ans. 7; see
also Final Act. 5 (“[t]he host interface contains logic to transfer information
to and from the host”).
However, the Examiner fails to direct our attention to disclosure
showing logic operable to send the claimed information to a host by the
memory controller. Although Figure 2 of Ito depicts two way
communication between the host 20 and the memory card 1 (which includes
memory controller 4), we do not discern anywhere in the citations provided
by the Examiner that the data or information provided from the controller to
the host is anything other than read data. See App. Br. 23, n. 52. Although
Ito discusses that the host may “recognize the file system” (col. 9,1. 57) and
“reference” a temporary file entry or flag (col. 14,11. 8, 10, 63, 65), we do
not agree with the Examiner that this necessarily means such data or
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Application 13/767,723
information is sent to the host by the controller, or that such logic is
necessarily present in the controller. Nor has the Examiner sufficiently
shown how the information described in the partition table corresponds to
the “state.” See, e.g., Spec. 176 (describing tracking a “unit state,” where
“this field can be used to store data indicated whether the [erase unit] is bad”
or “used to denote whether the [erase unit] contains valid host data, or is
otherwise available for allocation to the host or to the controller.”).
Because we agree with at least one of the arguments advanced by
Appellant, we need not reach the merits of Appellant’s other arguments.
Accordingly, for the foregoing reasons, we do not sustain the Examiner’s 35
U.S.C. § 103(a) rejection of independent claims 1, 22, 23, 29, and 37, and
their dependent claims 2, 3, 5, 7—21, 23—28, 30, 32—36, 38, and 39.
DECISION
For the above reasons, the Examiner’s 35 U.S.C. § 103(a) rejection of
claims 1—3, 5, 7—30, and 32—39 is reversed.
REVERSED
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