Ex Parte Kumar et al

Patent Trial and Appeal BoardFeb 15, 2019

14613933 (P.T.A.B. Feb. 15, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/613,933 02/04/2015 45851 7590 02/20/2019 Treyz Law Group 15279 N. Scottsdale Rd., Suite 250 Scottsdale, AZ 85254 FIRST NAMED INVENTOR Rajiv Kumar UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. A04596 8352 EXAMINER NGUYEN, VAN THU T ART UNIT PAPER NUMBER 2824 NOTIFICATION DATE DELIVERY MODE 02/20/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@treyzlawgroup.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte RAJIV KUMAR, WEI YEE KOA Y, and KUAN CHENG TANG Appeal2018-003980 Application 14/613,933 Technology Center 2800 Before ROMULO H. DELMENDO, LINDA M. GAUDETTE, and DEBRA L. DENNETT, Administrative Patent Judges. DENNETT, Administrative Patent Judge. DECISION ON APPEAL 1 STATEMENT OF THE CASE Appellant2 appeals under 35 U.S.C. Â§ 134(a) from a rejection of claims 1--4, 6-9, 13-18, and 20. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We AFFIRM-IN-PART. 1 In our Decision, we refer to the Specification filed February 4, 2015 ("Spec."); the Non-final Action dated October 6, 2016 ("Non-final Act."); the Appeal Brief filed March 20, 2017 ("Br."); and the Examiner's Answer dated May 19, 2017 ("Ans."). Appellant did not file a Reply Brief. 2 Appellant is applicant Altera Corporation, identified as the real party in interest. Br. 2. Appeal2018-003980 Application 14/613,933 The claims are directed to methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration. Independent claims 1, 8, and 16, reproduced below with key limitations italicized, illustrate the claimed subject matter: 1. An integrated circuit, comprising: a memory cell; a bit line that is coupled to the memory cell; a precharge transistor that is coupled to the bit line; a decoder for addressing the memory cell, wherein the decoder determines whether the memory cell is to be selected during a decode time period, and wherein the precharge transistor is turned off during the decode time period; and an additional bit line that is coupled to the memory cell and that is not connected to any precharge circuitry. 8. A method of operating an integrated circuit, comprising: during a decode time period, using a decoder circuit to address a memory cell; using a precharge circuit to precharge a bit line that is coupled to the memory cell; keeping the precharge circuit turned off during the decode time period; and after the bit line is precharged, asserting a word line signal to access the memory cell. 16. An integrated circuit, comprising: a first array of memory cells; a second array of memory cells; a word line that is coupled to the first array of memory cells and the second array of memory cells; 2 Appeal2018-003980 Application 14/613,933 first precharge circuits that are coupled to the first array of memory cells; second precharge circuits that are coupled to the second array of memory cells, wherein the first precharge circuits are activated to access at least one memory cell in the first array while the second precharge circuits are deactivated to reduce power consumption in the second array, and wherein the word line is driven high after the first precharge circuit is deactivated; and a row decoder that determines which row in the first and second arrays to access during a decode time period, wherein the first and second precharge circuits are turned off during the decode time period. Br. 15, 17-19 (Claims Appx). REFERENCES The Examiner relies on the following prior art in rejecting the claims on appeal: Rogers et al. ("Rogers") Hasegawa et al. ("Hasegawa") Houston Lin et al. ("Lin") Chong et al. (Chong") us 5,828,610 US 6,480,947 Bl US 8,064,271 B2 US 2013/0010544 Al US 2014/0286096 Al REJECTI0NS 3 Oct. 27, 1998 Nov. 12, 2002 Nov. 22, 2011 Jan. 10,2013 Sept. 25, 2014 The Examiner maintains and Appellant seeks review of the following rejections: (1) claims 1-3, 6, and 7 under 35 U.S.C. Â§ I02(a)(l) over Chong 3 Because this application was filed after the 16 March 2013, effective date of the America Invents Act, we refer to the AIA version of the statute. 3 Appeal2018-003980 Application 14/613,933 with support of Hasegawa or Houston; (2) claims 8, 9, 16, and 18 under 35 U.S.C. Â§ 102(a)(l) over Rogers; (3) claim 4 under 35 U.S.C. Â§ 103 over Chong in view of Lin; and (4) claims 13-15, 17, and 20 under 35 U.S.C. Â§ 103 over Rogers in view of Chong. Non-Final Act. 2-8; Br. 6-14. OPINION Rejection of claims 1-3, 6, and 7 as anticipated by Chong The Examiner rejects claims 1-3, 6, and 7 as unpatentable under 35 U.S.C. Â§ 102(a)(l) over Chong. Non-Final Act. 2--4. Appellant relies on the arguments offered in support of claim 1 to overcome the rejection of claims 2, 3, 6, and 7. Br. 6-9. Therefore, we confine our discussion to claim 1, which we select as representative pursuant to 3 7 C.F .R. Â§ 4I.37(c)(l)(iv). As provided by this rule, claims 2, 3, 6, and 7 stand or fall with claim 1. The Examiner finds that Chong discloses all elements of claim 1. Non-Final Act. 2-3. In addition, the Examiner finds that both Hasegawa and Houston disclose an additional bit line that may be coupled to the memory cell and not connected to any precharge circuity. Id. at 3. Appellant argues that Chong fails to disclose "an additional bit line that is coupled to the memory cell and that is not connected to any precharge circuitry." Br. 6. Appellant contends that Chong explicitly teaches precharging the bit line prior to a write operation. Id. at 7 ( citing Chong ,r 65). However, Appellant argues a different embodiment of Chong than that to which the Examiner directs us in the rejection. Specifically, Appellant argues that the text in paragraph 65 of Chong ( which concerns the 4 Appeal2018-003980 Application 14/613,933 embodiment illustrated in Fig. 7 of the reference) teaches precharging the bit line prior to a write operation. Br. 6. The Examiner's findings are based on the embodiment disclosed in Fig. 2 and paragraphs 44 and 45 of Chong. Non-Final Act. 2-3; Ans. 2. The Examiner emphasizes that "not connected" is a negative limitation which is met by Fig. 2 of Chong because it does not show ( and its description does not describe) a precharge operation on write bit line BL 122. Ans. 2-3. Figure 2 of Chong is reproduced below: 155 \ ~\;f<'(~S,:)' CELL; 16th 1,l!~Mlmv C:â‚¬Ll2 r=Q---k RBL,~;F>QM k 185 4 SO FIG.2 Figure 2 illustrates components provided in association with one column within a block structure in accordance with one of two alternative configurations of memory block structures that can be used to form a 5 Appeal2018-003980 Application 14/613,933 memory array of a memory device. Chong ,r 42. The top read bit line 1504 provides one input to the NAND gate 180. Id. The bottom read bit line 185 provides the second input, and will have the same arrangement of components connected to it as are shown in FIG. 2 in respect of the top read bit line 150. Id. A series of memory cells 100, 155, 160, and 165 are connected to the top read bit line. Id. Each memory cell has the form shown in detail with respect to the memory cell 100. Id. During a write operation directed to the memory cell 100, the write word line (WWL) signal will be asserted to tum on the pass gate transistors 115, 120. Id. Write driver circuitry will then control the voltages on the write bit lines 122, 124 in order to cause the required data value to be written into the memory cell, and at the end of the write operation the write word line signal will be de- asserted to tum off the pass gate transistors 115, 120, and hence isolate the data holding part of the cell formed by the inverters 105, 110 from the write bit lines 122, 124. Id. During a read operation, a signal on the read word line 145 will be asserted, turning on the transistor 140 or the coupling circuitry 130 for an addressed row of memory cells. Id. ,r 45. Prior to the read word line signal being asserted, the read bit line 150 will have been precharged to the logic one (Vdd) level using the precharge PMOS transistor 170. Id. Chong's Fig. 2 and related description demonstrate the presence of "an additional bit line that is coupled to the memory cell and that is not connected to any precharge circuitry," as required by claim 1. Thus, Appellant's arguments fail to identify any reversible error in the Examiner's 4 Labels to elements are presented in bold font, regardless of their presentation in the original document. 6 Appeal2018-003980 Application 14/613,933 rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011). We sustain the rejection of claim 1 as anticipated by Chong. 5 We sustain the rejection of claims 2, 3, 6, and 7 for the same reasons. Rejection of claim 4 as obvious over Chong in view of Lin The Examiner rejects claim 4 as unpatentable under 35 U.S.C. Â§ 103 over Chong in view of Lin. Non-Final Act. 6-7. The Examiner finds that Lin teaches a word line signal wherein the word line is coupled to the memory cell, and wherein the precharge transistor is turned on while the work line signal is asserted. Id. at 7 (referring to the additional limitation of claim 4). Appellant argues that Lin does not cure the deficiencies of Chong. Br. 9. As explained in relation to claim 1, Appellant fails to show any deficiencies in the rejection over Chong. We, therefore, sustain the rejection of claim 4 as obvious over Chong in view of Lin. Rejection of claims 8, 9, 16, and 18 as anticipated by Rogers The Examiner rejects claims 8, 9, 16, and 18 as unpatentable under 35 U.S.C. Â§ 102(a)(l) over Rogers. Non-Final Act. 4--6. The Examiner finds that Rogers Figs. 7 and lOA-lOF and their related text disclose all elements of these claims. Id. Appellant argues that Rogers fails to disclose "keeping the precharge circuit turned off during the decode time period," as required by claims 8 5 Because the rejection is under 35 U.S.C. Â§ 102(a)(l), we focus on Chong. We need not address the Examiner's finding that Hasegawa and Houston support the rejection. See Non-Final Act. 3. 7 Appeal2018-003980 Application 14/613,933 and 9, and "wherein the first and second precharge circuits are turned off during the decode time period," as required by claims 16 and 18. Br. 10-12. Appellant contends that Figs. 3C, 3D, lOC, and lOD of Rogers show that both address decode signal and PCH are asserted during each of the clock cycles, proving that the precharge transistor is turned on during the decode time period. Id. at 11. During prosecution, "claims ... are to be given their broadest reasonable interpretation consistent with the specification, and ... claim language should be read in light of the specification as it would be interpreted by one of ordinary skill in the art." In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (quoting In re Bond, 910 F.2d 831, 833 (Fed. Cir. 1990)). We interpret "keeping the precharge circuit turned off during the decode time period" ( claim 8) and "wherein the first and second precharge circuits are turned off during the decode time period" ( claim 16) as requiring that the precharge circuit is turned off during the entirety of the decode time period. See Spec. 3, 11. 6-7; 13, 11. 14. Rogers Figs. 3A-F illustrate a timing diagram of a conventional RMA; Figs. lOA-F illustrate a timing diagram of the preferred embodiment of Rogers' invention. See Rogers Figs. 3A-F and lOA-G; col. 6, 11. 25, 30-31, 48-50. In the Non-Final Office Action, the Examiner cites to Figs. lOA-lOF of Rogers, reproduced below: 8 Appeal2018-003980 Application 14/613,933 FIG._ 10A CLOCK FIG._ 108 ADD1NPUT672 ~ FIG._ 10C ADDRESS DECODE ~ 660,680 F/G._ 10D PCH611 __flJU9_ FIG._ 10E AYS671 ~ FIG._ 10F AWL661 ~ Figures 1 OA-1 OF depict read operation precharge circuit time according to the preferred embodiment in Rogers. Rogers col. 6, 11. 48-50. In response to Appellant's argument that Figs. IOC and IOD (and Figs. 3C and 3D) show the precharge transistor is turned on for part of the decode time period, the Examiner submits that timing diagrams, such as Figs. 1 OA-1 OF are not required to be precise, and the text descriptions of the figures are given more weight in teaching the claimed limitations. Ans. 6, 7. The Examiner notes that Rogers describes read operation details as follows: Just prior to the rising edge of clock cycle 1 (FIG. IOA), the ADD[] input is received as ADDI (FIG. IOB). During the first half of the clock cycle, the address ADD input [] is decoded in row decoder [] and column decoder [] as DECL illustrated in FIG.lOC. The upper address bits of ADD input [] enter the row decoder [] to select a single RAM row and activate the Read-Word-Line signal RWL [] of the selected row, asWl in FIG. IOF. The lower address bits of ADD input [] enter the Column Decoder [] to select one RAM column [] and to activate the Read-Column-Select signal RYS [] of the selected column, as YI in FIG. 1 OE. Also, during the second half (i.e., low phase) of clock cycle 1, PCH [] will be asserted 9 Appeal2018-003980 Application 14/613,933 high (as Pl in FIG. lOD), to activate bit line precharge NMOS transistor. Id. at 6-7 (Rogers, col. 10, 11. 17-31 (emphasis per Examiner)). We find no justification to discount the disclosures shown in Figs. lOA-lOF, or to doubt their reliability. Moreover, the text that the Examiner quotes does not contradict the information disclosed in Figs. 1 OA-1 OF. One of ordinary skill in the art at the time of the invention would have interpreted Rogers as teaching that the precharge transistor is turned on during the second half of each clock cycle. This teaching directly conflicts with the requirements of independent claims 8 and 16, and their dependent claims 9 and 18. A reference must disclose, with sufficient specificity, or clearly and unequivocally, every element of the claimed invention arranged as recited in the claim to be anticipatory. Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir. 2001). Because Rogers does not teach every element of claims 8, 9, 16, and 18, we do not sustain the rejection of these claims as anticipated by Rogers. Rejection of claims 13-15, 17, and 20 as obvious over Rogers in view of Chong The Examiner rejects claims 13-15, 17, and 20 as unpatentable under 35 U.S.C. Â§ 103 over Rogers in view of Chong. Non-Final Act. 7-8. Claims 13-15 depend from claim 8; claims 17 and 20 depend from claim 16. Br. 18-20 (Claims Appx). The Examiner relies on Chong for teaching the additional limitations recited in the dependent claims. See Non-Final Act. 7-8. 10 Appeal2018-003980 Application 14/613,933 Appellant contends that Chong does not remedy the deficiencies of Rogers in teaching the limitations of independent claims 8 and 16. Br. 13- 14. We agree. The Examiner fails to establish a prima facie case of obviousness of claims 13-15, 17, and 20. We do not sustain the rejection of these claims. DECISION The rejections of claims 1-3, 6, and 7 as anticipated by Chong, and of claim 4 as obvious over Chong in view of Lin are affirmed. The rejections of claims 8, 9, 16, and 18 as anticipated by Rogers, and of claims 13-15, 17, and 20 as obvious over Rogers in view of Chong are reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a)(l )(iv). AFFIRMED-IN-PART 11