Ex Parte Kottapalli

Patent Trial and Appeal Board

Dec 27, 2012

11638315 (P.T.A.B. Dec. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/638,315 12/12/2006 Sailesh Kottapalli Intel 2207/1012202 2284
25693 7590 12/28/2012
KENYON & KENYON LLP
1801 PAGE MILL ROAD
Suite 210
PALO ALTO, CA 94304-1216
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
12/28/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte SAILESH KOTTAPALLI
____________

Appeal 2010-006995
Application 11/638,315
Technology Center 2100
____________

Before SCOTT R. BOALICK, BARBARA A. BENOIT, and
JENNIFER L. McKEOWN, Administrative Patent Judges.

BENOIT, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-9, all the claims pending in the application. We have jurisdiction
under 35 U.S.C. § 6(b). We affirm.

Appeal 2010-006995
Application 11/638,315

2
STATEMENT OF THE CASE
Appellant’s invention relates to design of multithreaded processors
and how to redirect or re-steer a processor to the proper instruction in a
stream of instructions if an inactive thread becomes active. See generally
Abstract; Spec. 5. Claim 1 is illustrative and reads as follows, with key
disputed limitations emphasized:
1. A processor comprising:
a first multiplexer to receive a first instruction thread;
a second multiplexer to receive a second instruction thread;
a first storage element to store a set of instruction pointers associated
with the first instruction thread from the first multiplexer if the first thread is
inactive;
a second storage element to store a set of instruction pointers associated
with the second instruction thread from the second multiplexer if the second
thread is inactive;
a first inactive thread re-steer logic to cause the first multiplexer to
receive the instruction pointers associated with the first thread if the first
thread becomes active;
a second inactive thread re-steer logic to cause the second multiplexer to
receive the instruction pointers associated with the second thread if the
second thread becomes active.
The Rejections
1. The Examiner rejected claims 1-4 and 9 under 35 U.S.C. § 102(a) as
anticipated by Appellant’s admitted prior art. Ans. 3-4.
2. The Examiner rejected claims 5-8 under 35 U.S.C. § 103(a) as
unpatentable over the AAPA. Ans. 4-6.

ANALYSIS
The Examiner finds that Appellant’s Figure 2 and paragraph 0005
(collectively, Appellant’s admitted prior art or “AAPA”) disclose every
recited feature of independent claim 1. Ans. 3 (citing Spec. ¶ 0005, Fig. 2).
Appeal 2010-006995
Application 11/638,315

3
The Examiner maps the recited re-steer logic to re-steer components 224,
226, 228, 230, and 232; the recited storage elements to storage components
248 and 250; and the recited first and second multiplexers to multiplexers
218 and 220, respectively. Ans. 3; see also Spec. ¶ 0022 (disclosing 224,
226, 228, 230, and 232 as re-steer logic components).
We are not persuaded by Appellant’s arguments (App. Br. 4-5; Reply
Br. 2-4) that the AAPA does not teach the limitation “a first inactive thread
re-steer logic to cause the first multiplexer to receive the instruction pointers
associated with the first thread if the first thread becomes active.” Appellant
asserts that, because the AAPA only discloses capturing the re-steer
information on the inactive thread, the re-steer logic does not cause the first
multiplexer to receive the instruction pointers if the inactive thread becomes
active. App. Br. 4-5. As explained by the Examiner in response to
Appellant’s arguments, the AAPA discloses that the re-steer logic, by
temporarily storing the instruction pointers in the storage elements, causes
the multiplexers to receive the instruction pointers saved in the storage
components if that thread becomes active again. Ans. 7.
We are not persuaded of error in the Examiner’s position. Although
we agree with Appellant that the AAPA discloses that the storage elements
in Figure 2 capture the re-steer information on the inactive thread, we
disagree with Appellant that the disclosed re-steer logic does not cause the
first multiplexer to receive the instruction pointers if the inactive thread
becomes active. For example, and as cited by the Examiner (Ans. 3),
paragraph 0005 discloses the purpose of capturing the re-steer information in
storage elements is for redirection to point to the proper instruction and the
re-steer information would be lost during inactivity of the thread without the
Appeal 2010-006995
Application 11/638,315

4
storage elements. Spec. ¶ 0005. Moreover, the Specification also states
with regard to Figure 2 that the re-steer information is fed from the re-steer
logic 224, 226, 228, 230, and 232 to the multiplexer 218 and is allowed by
the common multiplexer 246 to pass to the processor pipeline. Spec. ¶ 0021;
see also Ans. 3 (citing Spec. ¶ 0005; Fig. 2). Identity of terminology
between an applied reference and claimed limitation is not required to
anticipate claim 1. See In re Bond, 910 F.2d 831, 832-33 (Fed. Cir. 1990)
(indicating that anticipation does not require an ipsissimis verbis test).
As such, we are not persuaded of error in the Examiner’s finding that
the AAPA discloses the recited limitation “a first inactive thread re-steer
logic to cause the first multiplexer to receive the instruction pointers
associated with the first thread if the first thread becomes active” or the
similar limitation “a second inactive thread re-steer logic to cause the second
multiplexer to receive the instruction pointers associated with the second
thread if the second thread becomes active.”
For the first time in the Reply Brief and in response to the Examiner's
comments that Appellant interprets the claims too narrowly (Ans. 7),
Appellant argues that the AAPA does not disclose the disputed limitation
because the AAPA is in a different context than the context of the claims.
Reply Br. 2-3. For support, Appellant points to a particular embodiment in
the Specification (citing Spec. ¶¶ 0012, 0024 (describing Fig. 3)) and the
Specification’s discussion of the invention’s advantage of reducing the
number of hardware components over conventional designs, such as shown
in Figure 2 (citing Spec. ¶¶ 0020, 0023). Reply Br. 2-3.
Appellant’s argument that the Specification limits the plain language
of the claims is unavailing. It is well-established that we are to apply the
Appeal 2010-006995
Application 11/638,315

5
broadest reasonable meaning to the claim language, taking into account any
definitions presented in the Specification. See In re Am. Acad. of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Appellant has not pointed to
any definitions in the Specification, and we decline to read limitations into a
claim from an embodiment described in the Specification. Id. This is
appropriate because Appellant has the opportunity to amend the claims to
obtain more precise coverage. Id.
Accordingly, we sustain the rejection of independent claim 1 as
anticipated by the AAPA, as well as claims 2-4 and 9, not argued separately
with particularity. For similar reasons, we also sustain the rejection of
dependent claims 5-8, which were not argued separately with particularity,
as obvious over the AAPA.

CONCLUSION
The Examiner did not err in rejecting claims 1-4 and 9 under § 102 or
in rejecting claims 5-8 under § 103.

ORDER
The Examiner’s decision rejecting claims 1-9 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

babc