Ex Parte Kolodny et alDownload PDFPatent Trials and Appeals BoardJun 27, 201914219030 - (D) (P.T.A.B. Jun. 27, 2019) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/219,030 69054 7590 RECHES PA TENTS HaArba"a Towers North Tower TEL A VIV, 6473925 ISRAEL 03/19/2014 07/01/2019 FIRST NAMED INVENTOR A vinoam Kolodny UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 8413-US 4549 EXAMINER PAN, DANIEL H ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 07/01/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): OREN@I-P.CO.IL MAIL@I-P.CO.IL eofficeaction@appcoll.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte A VINOAM KOLODNY, URI WEISER, and SHARAR KV ATINSKY 1 Appeal2018-008505 Application 14/219,030 Technology Center 2100 Before BRADLEY W. BAUMEISTER, SHARON PENICK, and RUSSELL E. CASS, Administrative Patent Judges. CASS, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final rejection of claims 1-3, 5-17, and 19-28, which constitute all the claims pending in this application. Appeal Br. 1. 2 We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. 1 Appellants list the Technion Research & Development Foundation Ltd. as the real party in interest. Appeal Brief filed July 31, 201 7 ("Appeal Br."), 3. 2 Rather than repeat the Examiner's positions and Appellants' arguments in their entirety, we refer to the above mentioned Appeal Brief, as well as the following documents for their respective details: the Final Action mailed August 31, 2016 ("Final Act.") and the Examiner's Answer mailed June 1, 2018 ("Ans."). Appeal2018-008505 Application 14/219,030 THE INVENTION Appellants' invention is directed using multi threading processors to improve performance in a single core. Spec ,i 2. Appellants' Specification explains that one existing multithreading technique is "Switch on Event multithreading (SoE MT), ... where a thread runs inside the pipeline until an event occurs (e.g., a long latency event like a cache miss) and triggers a thread switch." When this happens, the "state of the replaced thread is maintained by the processor, while the long latency event is handled in the background." Id. "While a thread is switched, the in-flight instructions are flushed," and the "time required to refill the pipeline after a thread switch is referred to as the switch penalty," which is "usually relatively high." Id. The invention seeks to overcome this problem using "a novel microarchitecture" called "Continuous Flow Multithreading (CFMT)." Id. ,i 28. The Specification explains that "[t]he primary concept of CFMT is to support SoE MT for a large number of threads through the use of multistate pipeline registers (MPRs ). " These MPRs "store the intermediate state of all instructions of inactive threads, eliminating the need to flush the pipeline on thread switches," giving the machine" higher energy efficiency while improving the performance as compared to regular SoE MT." Id. The Specification further explains that "[t]he development of new memory technologies, such as RRAM (ResistiveRAM) and STT-MRAM (Spin-Transfer Torque Magnetoresistive RAM), enables MPRs since these devices are located in metal layers above the logic cells and are fast, dense, and power efficient." Id. ,i 30. The Specification explains that "[t]hese memory technologies are referred to as memristors." Id. 2 Appeal2018-008505 Application 14/219,030 THE EXAMINER'S REJECTION Claims 1-3, 5-17, and 19-28 stand rejected as being unpatentable over Shen (2009/0172362 Al; published July 2, 2009) in view of Beckmann (2012/0254541 Al; published Oct. 4, 2012). Final Act. 2. ANALYSIS Appellants make five separate arguments directed to different claims under rejection, which we address in tum. I. Claims 1 and 15 Appellants' first argument is directed to claims 1 and 15, which they argue together. Claim 1 is illustrative: 1. A device that comprises: a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions. Appeal Br. 19 (Claims Appendix). 3 Appeal2018-008505 Application 14/219,030 The Examiner finds that Shen teaches the limitations of claim 1 except that "Shen does not specifically show his buffers as memristor based registers." Final Act. 3. "However," the Examiner finds, "Be[ck]mann teaches memristor based registers," pointing to Beckmann's disclosure of passive variable resistive memory (PVRM) as memristor memory. Id. ( citing Beckmann ,-J 32). As to motivation to combine, the Examiner states as follows: It would have been obvious to one of ordinary skill in the art to use Beckmann in Shen for including the memristor registers as claimed because one of ordinary skill in the art should recognize the application of a known technique (such as the memristor registers taught by Beckmann) to a known device (such as the pipelined system of Shen) for reducing the overall power of the pipeline system and for replacing the conventional memory/registers (see MPEP 2143 KSR Example D; see also Beckmann para [0033] [0036]). Final Act. 3. Appellants respond by arguing that there was no motivation to combine Beckmann with Shen. Appeal Br. 10. Appellants argue that the present application "aims to reduce the time penalty associated with thread switching, while Shen "aims to change the order of [the] selected thread over time." Appeal Br. 10 ( citing Spec. ,-J 2; Shen ,-J 4). Appellants further argue that the "only reference [in] ... Beckmann to threading is included in paragraph [0047] and refers to a FENCE instruction that prevents unpredictable behavior that occurs when memory operations are reordered across multiple threads of instructions." Appeal Br. 11 ( citing Beckmann ,-J 47). Thus, Appellants contend, "Beckmann and Shen aim[] to solve problems that are not related to each other and neither one addresses the problem mentioned by the office (for reducing the overall power of the 4 Appeal2018-008505 Application 14/219,030 pipeline system and for replacing the conventional memory/registers)." Appeal Br. 11 ( emphasis omitted). As a result, according to Appellants, "[b Joth Beckmann and Shen do not solve the problem that is solved by the current application" and "there is no motivation to add the teachings of these references." Id. at 12. In the Examiner's Answer, the Examiner states that "the memristor is known in the art, as admitted by appellant, for fast, dense, power efficiency." Ans. 15 ( citing Spec. ,i 30). The Examiner finds a motivation to combine Shen and Beckmann because both references "are directed to solve the same problem of reducing power." Id. at 16. More specifically, the Examiner finds that: Shen teaches that an integer execution unit [212] can be idled or used to execute instruction operations from other thread while another integer unit [214] continue execute instructions by an original thread (see para [0053]). Shen teaches also that the unused integer unit can be disabled so as to reduce the power consumption (para [0026]). In addition to Shen, Beckmann teaches by using the memristor (resistive), in contrast to the charge-based memory, ( e.g. see PVRAM in para [0033], already cited on the record), it retains the state information after a power loss or power cycle. Therefore, by avoiding the recharge of the memory (i.e. no need for recharging), the memristor saves [] power. Id. at 15-16. Here, the central issue is whether motivation existed to combine Shen and Beckman. We determine that the Examiner has established a prima facie case that such a motivation existed. Appellants acknowledge that memristors were known in the art "as potential replacements for the traditional SRAM/DRAM-based memory 5 Appeal2018-008505 Application 14/219,030 system to overcome scaling issues, such as greater leakage current," or that memristors were known to be "dense, fast, and power efficient." Spec. ,i,i 30, 47-48. Beckmann also teaches that memristors had the advantage of being "non-volatile" so that they "retain state information following a power loss or power cycle." Beckmann ,i 33. Beckmann further points to the advantages of such "new types of storage" over "traditional non-volatile memory," which has "relatively slow access times." Id. ,i,i 3-4. Shen, in tum, teaches use of registers in a pipeline execution unit that can be idled while another execution unit is used to execute instructions from another thread. Shen ,i,i 53. We agree with the Examiner that a person of ordinary skill would have been motivated to use the non-volatile memristor memory of Beckmann for the registers of Shen in order to save power (by not having to supply power to the registers when they are idle) and to increase speed over conventional non-volatile memory. Doing so merely would have constituted an application of a known technique (using the memristors of Beckmann) to a known device (the pipelined system of Shen) to achieve predictable results (improving the speed and power consumption of the overall system). See MPEP § 214 3. Appellants have not demonstrated that the use of memristors in a pipelined system was in any way unpredictable or counterintuitive. We also find unpersuasive Appellants' arguments that there would have been no motivation to combine Shen and Beckmann because the aims of each reference were different from those of the present invention. See Appeal Br. 10. The teaching of the prior art "is not limited to the specific invention disclosed," and "the use of patents as references is not limited to what the patentees describe as their own inventions." In re Kahn, 441 F.3d 6 Appeal2018-008505 Application 14/219,030 977, 990 (Fed. Cir. 2006) (citing In re Heck, 699 F.2d 1331, 1333 (Fed. Cir. 1983). Moreover, "[a]s long as some motivation or suggestion to combine the references is provided by the prior art taken as a whole, the law does not require that the reference be combined for the reasons contemplated by the inventor." In re Beattie, 974 F.2d 1309, 1312 (Fed. Cir. 1992) (cited in Kahn, 441 F.3d at 990). Appellants do not argue that Shen or Beckmann teach away from the claimed invention, and our review of the references does not reveal any disclosure that would qualify as a teaching away. Moreover, the fact that the aim of the Beckmann invention was different from the aim of the Shen invention does not prevent a determination of obviousness where, as here, a person of ordinary skill would have had a reason or motivation to combine the references, and the combination meets all of the elements of the claim. See id. Consequently, we affirm the Examiner's rejection of claim 1, and of claim 15, which includes similar limitations and which Appellants do not argue separately. See Appeal Br. 12. We also affirm the Examiner's rejection of claims 2, 3, 7, 8, 10-12, 14, 16, 17, 20-22, 24-26, and 28, which are dependent on claims 1 or 15 and which Appellants do not argue separately. See id. II. Claim 5 and 19 Appellants' second argument is directed to claims 5 and 19. Claim 5 is illustrative and is reproduced below with claim 3, upon which claim 5 depends: 3. The device according to claim 1, wherein the memristor based registers comprise resistive memory elements. 7 Appeal2018-008505 Application 14/219,030 5. The device according to claim 3, wherein the resistive memory elements are positioned directly above portions of the set of multiple pipeline stages. Appeal Br. 19 (Claims Appendix). The Examiner finds that Shen teaches claim 5 's limitation that the memory elements "are positioned directly above portions of the set of multiple pipeline stages," pointing to Figure 8 showing buffers 824 and 826 as being "both input and output ports of the pipeline stages." Final Act. 4. The Examiner further states that the claims do not recite the meaning of the term "above," and that the claims do not show the specific layers of the memristor elements described in the Specification. Ans. 16. Appellant argues that the prior art is deficient because Figure 8 of Shen, upon which the Examiner relies, "does not provide the physical arrangement of the different elements of Shen and especially does not teach or suggest that the resistive memory elements are positioned directly above portions of the set of multiple pipeline stages." Appeal Br. 13 ( emphasis omitted). We agree with Appellants that the Examiner has failed to establish that the prior art teaches resistive memory elements that are "positioned directly above" portions of the set of multiple pipeline stages, as claim 5 requires. The ordinary meaning of the term "positioned directly above" indicates a physical location of the resistive memory elements directly over the pipeline stages. This is consistent with Appellants' Specification, which in Figure 6 shows the resistive memory elements physically located over the pipeline stages. Figure 6 is reproduced below: 8 Appeal2018-008505 Application 14/219,030 74 73 72 .. 71 11 40(1.4) 40(1,t) FIG.6 More specifically, Figure 6 shows "layers 40( 1, 1 )-40( 1, 4 )" physically located directly above "flip flops (31(1) of pipeline stage 30(a)." Spec. ,-J 53; Fig. 6. Consequently, both the ordinary meaning of the claim language and the specification require that the resistive memory elements be in a physical position higher than and directly over the multiple pipeline states. Figure 8 of Shen, upon which the Examiner relies, does not show this physical relationship. Figure 8 is reproduced below: 9 Appeal2018-008505 Application 14/219,030 Fl!"EllNE STAGE B PWEUNS: STAGE C 1a~4) itO~) t----·~.A-~ _ ..---, r-------.._j<, ... ""·------, --------------------------------------- ,-inia FIG. 8 Figure 8 shows the processor pipeline with pipeline stages A, B, and C, and substages AO, Al, A2, BO, Bl, B2, etc. The Examiner relies on registers 824 and 826 of Figure 8, which are stated to be "both input and output ports of the pipeline stages." Final Act. 4. But the Examiner does not point to anything in Shen that indicates that these registers are located in a physical position directly above the pipeline stages. Consequently, the Examiner has not established that Shen teaches or suggests this limitation, so we reverse the rejection of claim 5. We also reverse the rejection of claim 19, which includes similar limitations and was argued on the same basis. See Appeal Br. 14. III. Claim 6 Appellants' third argument is directed to claim 6, which recites as follows: 6. The device according to claim 1, wherein a duration of the thread switch does not exceed a time required to re-fill the pipeline. Appeal Br. 19 (Claims Appendix). In rejecting of claim 6, the Examiner relies on paragraph 63 of Shen, which teaches that "each pipeline stage can independently select between 10 Appeal2018-008505 Application 14/219,030 threads." Final Act. 4. The Examiner also relies on Figure 9 of Shen, which is reproduced below: C¥ClfS K-->Kt2 CYCLES b>U-Z CYCLfS, !il-)'~f+l S:U~Cl l1,T~l~ "it~"'"'V'"'""''"'"'"'"'V"........., i i ~ : fi\2) l'1i~l l T~(2) t *t T~i) • T~~) T1Pi s-,.,.,.,.,.,, __ ,.,.,.,.,.,.,.,i ..,.,.,.,.,.,.,1 -~ ,.,.,.,.,.,.,,,'_.,.,.,_..,.,.,, SELECT T0 l~ T, \ ' ~ ~ ~ : r1is1 t1H1 P\tl}: 111 r~~j f1W T1lH •· l~\~} h!1} T,i.;~J ....._...,._......._~ ........,~ ~ ................ = _....._..., FIG .. 9 1 f 900 .) Figure 9 shows the processing of pipeline for threads To and T 1 at substages Ao-C2 (which the Examiner refers to as "sub-pipelines") for specific processor cycles. Shen ,i,i 14, 59. The Examiner finds that thread T 1 at sub-pipeline Ao is switched to To at sub-pipeline A1. Ans. 16. The Examiner further finds that the cycle time occupied by T 1 at Ao and To at A1 together (Ao+ A1) is smaller than the full cycle time for sub-pipelines Ao, A1 and A2 in combination. Therefore, the Examiner determines, the time for cycles occupied in substages Ao+A1 (which includes a thread switch) does not exceed Ao+A1+A2, the time required to refill the pipeline. Id. Appellants argue that "paragraph[] [0063] of Shen does not mention any element of claim 6 - and is irrelevant." Appeal Br. 14. We agree with the Examiner that Figure 9 of Shen would have suggested to a person of ordinary skill that the time required to switch from one thread to another (such as switching from T1 to To between substages Ao and A1) is less than the time needed to refill the entire pipeline (the time for substages Ao+A1+A2). This is because the thread switch only takes up a 11 Appeal2018-008505 Application 14/219,030 portion of the cycles for a pipeline stage, but the time needed to refill a pipeline stage takes all of the cycles of that pipeline stage. As to Appellants' argument that "paragraph[] [0063] of Shen does not mention any element of claim 6 - and is irrelevant, merely reciting limitations of claims and asserting that the prior art does not disclose the limitations does not provide effective argument for patentability of those claims. See 37 C.F.R. § 41.37(c)(l)(iv); In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (holding that the Board reasonably interpreted 37 C.F.R. § 41.37(c)(l)(vii) (predecessor to§ 41.37(c)(l)(iv)) to require "more substantive arguments in an appeal brief than a mere recitation of the claim elements and a naked assertion that the corresponding elements were not found in the prior art."). Consequently, we affirm the Examiner's rejection of claim 6. IV. Claims 9 and 23 Appellants' fourth argument is directed to claims 9 and 23. Claim 9 is illustrative, and it is reproduced here with claim 8 (upon which claim 9 depends): 8. The device according to claim 1, wherein the storage of the state of the first thread of instructions at the multiple memristor based registers is preceded by extracting the state of the first thread of instructions from the set of multiple pipeline stages. 9. The device according to claim 8, wherein an aggregate duration of the extracting of the state of the first thread of instructions and the storage of the state of the first thread of instructions exceeds a duration of the provision of the state of the other thread of instructions. Appeal Br. 19-20 (Claims Appendix). 12 Appeal2018-008505 Application 14/219,030 In rejecting claim 9, the Examiner again relies on Figure 9 of Shen, finding that: As to claim 9, Shen teaches wherein an aggregate duration of the extracting of the state of the first thread of instructions and the storage of the state of the first thread of instructions ( see the processing cycles K-K + 2 for selecting the t[h ]read To in [ 0060]) exceeds a duration of the provision of the state of the other thread of instructions [T1] (see fig.9 selecting cycles ofK-K+2). Final Act. 5. The Examiner also finds that Figure 9 shows that "To at A1 and To at A2 occupy aggregated cycles (A1+A2) which is greater than the cycle occupied by T 1 at Ao." Ans. 17. The Examiner further reasons that "[ e Jach stage has the extraction (e.g. output) and storage (e.g. input) of [a] thread state because of the input buffers and output buffers provided at each of the stages." Id. Appellants respond that "Figure 9 is not an exact timing diagram and does not teach or suggest the subject matter of claim 9." Appeal Br. 16. We conclude that the Examiner has established a prima facie case of obviousness as to claim 9, and that Appellants have not overcome it. We agree with the Examiner that Figure 9 and the accompanying description of Shen would have suggested to one of ordinary skill that the aggregate duration of the output of the state of the first thread of instructions (TO in A 1 and TO in A2) would exceed the amount of time it would take to present a state of another thread of instructions, which would take place within the duration of one of the sub-cycles AO, Al, or A2 of the pipeline. Even though Figure 9 is not an exact timing diagram, it does indicate that a common sub-cycle time is required by each processing stage. See Shen ,-J 5 8 ( referring to the "number of cycles or substages needed to execute the instruction operation"). One of skill would have been able to conclude 13 Appeal2018-008505 Application 14/219,030 from this that presenting a state of another thread of instructions would have taken less time than outputting an entire first thread of instructions. Appellants provide no argument or evidence to the contrary other than to merely assert that Figure 9 is not an exact timing diagram, which is insufficient to overcome the Examiner's prima facie case of obviousness. See Appeal Br. 16. Consequently, we affirm the Examiner's rejection of claim 9, and of claim 23, which includes similar limitations and was rejected on substantially the same basis. See Final Act. 9. V. Claims 13 and 2 7 Appellants' fifth argument is directed to claims 13 and 27. Claim 13 is illustrative and is reproduced herein with claim 10 (upon which claim 13 depends): 10. The device according to claim 1, wherein the multiple memristor based registers are arranged to store a state of each thread of instructions out of multiple other threads of instructions that differ from the first thread of instructions; and wherein the control circuit is arranged to control thread switches between any instructions out of the first thread of instructions and any one of the other threads of instructions. 13. The device according to claim 10, wherein the multiple memristor based registers comprises multiple layers, wherein each layer is dedicated for storing the status of a single other thread of instructions. Appeal Br. 20 (Claims Appendix). The Examiner finds that Beckmann teaches memristors that include an array of layers. Final Act. 6 ( citing Beckmann ,i 62). Specifically, the Examiner finds that "Beckmann teaches memristor memory cell ( one bit) includes a memory region ( e.g. a layer of Ti02) between two metal contacts (see para [0062])" and "a memristor secondary layer [Ti02-x] (see 14 Appeal2018-008505 Application 14/219,030 para [0066])." Ans. 17. "Therefore," the Examiner concludes, Beckmann "teaches multiple memristors based on registers compris[ing] multiple layers." Id. Appellants respond that paragraph 62 of Beckmann teaches "a cross bar that is a SINGLE LAYER of memristors." Appeal Br. 17. Appellants further argue state that"[ e ]specially - Beckmann fails to teach or suggest the multiple memristor based registers comprises multiple layers, wherein each layer is dedicated for storing the status o(a single other thread of instructions." Id. We agree with Appellants that the Examiner has failed to establish obviousness based on Shen and Beckmann. The Examiner has not sufficiently established that either Shen or Beckmann teaches multiple memristors with multiple layers, in which "each layer is dedicated for storing the status of a single other thread of instructions." The Examiner only points to Beckmann as teaching multiple memristors with multiple layers, without establishing how "each layer is dedicated for storing the status of a single other thread of instructions." We, therefore, reverse the Examiner's rejection of claim 13, and of claim 27, which recites similar limitations and was rejected on substantially the same basis. See Final Act. 10. DECISION We affirm the Examiner's rejection of claims 1-3, 6-12, 14-17, 20- 26, and 28. We reverse the Examiner's rejection of claims 5, 13, 19 and 27. 15 Appeal2018-008505 Application 14/219,030 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F. R. § l .136(a). AFFIRMED-IN-PART 37 C.F.R. § 41.50(b) 16 Copy with citationCopy as parenthetical citation