Ex Parte Koh et al

Patent Trial and Appeal Board

Nov 23, 2012

09802857 (P.T.A.B. Nov. 23, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
09/802,857 03/12/2001 Akihiko Koh SON-2047 3304
23353 7590 11/23/2012
RADER FISHMAN & GRAUER PLLC
LION BUILDING
1233 20TH STREET N.W., SUITE 501
WASHINGTON, DC 20036
EXAMINER
YIGDALL, MICHAEL J
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte AKIHIKO KOH, TSUTOMU SAMPEI,
NOBUHISA WATANABE, and AKIHIRO KIKUCHI
____________

Appeal 2011-011849
Application 09/802,857
Technology Center 2100
____________

Before JOSEPH F. RUGGIERO, JOHN A. JEFFERY, and
ANDREW CALDWELL, Administrative Patent Judges.

RUGGIERO, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 63-69. Claims 1-62 have been canceled (App. Br. 4). An oral
hearing was conducted on this appeal on November 6, 2012. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm. .
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Rather than reiterate the arguments of Appellants and the Examiner,
reference is made to the Appeal Brief (filed Mar. 10, 2011), the Answer
(mailed May 23, 2011), and the Reply Brief (filed July 12, 2011). Only
those arguments actually made by Appellants have been considered in this
decision. Arguments which Appellants could have made but chose not to
make in the Briefs have not been considered and are deemed to be waived
(see 37 C.F.R. § 41.37(c)(1)(vii)).
1

Appellants’ Invention
Appellants’ invention relates to a data processing apparatus including
at least a central processing unit (CPU) and a memory providing programs
for the CPU which enables the correcting of bugs in the programs stored in
the memory after manufacture. See generally Spec. 1:5-10.
Claims 63 and 64 are illustrative of the invention and read as follows:
63. A data processing apparatus comprising:
a central processing unit configured to initiate execution of an
interrupt processing routine upon a transition of an interrupt request signal, a
first signal and a second signal being input to said central processing unit as
said interrupt request signal,
wherein said central processing unit executes a program code, said
program code being stored in memory at a program address,

1
Appellants filed an amendment after final Office action concurrently with
the filing of the Appeal Brief. This amendment canceled claims 53-62,
placed claims 63 and 64 in independent form, and added new claims 70-78.
This amendment was entered by the Examiner as indicated in the Advisory
Action mailed May 18, 2011. Appellants indicate that claims 70-78 are not
presented for appeal (App. Br. 4). Although the Examiner indicated in the
Advisory Action how claims 70-78 would have been rejected if they were
presented on appeal, there is no existing rejection of claims 70-78 on the
record and, accordingly, claims 70-78 are not before us.
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wherein said memory is random access memory,
wherein a counter register is located within said random access
memory, said counter register being incremented when said program address
coincides with a first bug address or a second bug address.

64. A data processing apparatus comprising:
a central processing unit configured to initiate execution of an
interrupt processing routine upon a transition of an interrupt request signal, a
first signal and a second signal being input to said central processing unit as
said interrupt request signal,
wherein said central processing unit executes a program code, said
program code being stored in memory at a program address,
wherein said first signal indicates when said program address and a
first bug address coincide, said second signal indicating when said program
address and a second bug address coincide.

The Examiner’s Rejections
The Examiner relies on the following prior art references to show
unpatentability:
Miyazawa US 5,357,627 Oct. 18, 1994
Suzuki US 5,784,537 July 21, 1998
Claims 64-69 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Suzuki.
Claim 63 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Suzuki in view of Miyazawa.

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ANALYSIS
35 U.S.C. § 102(b) REJECTION
Claims 64 and 65
Appellants argue, with respect to independent claim 64, that Suzuki
does not disclose a first and a second signal being input to a CPU as an
interrupt request signal. According to Appellants, Suzuki’s PC comparison
register 20 compares a stored value with an address value and, upon
coincidence, outputs to the CPU 14 an interruption request signal, not first
and second signals as claimed (App. Br. 12; Reply Br. 7-8).
We do not agree with Appellants. We find no error in the Examiner’s
determination that the claimed “first signal” and “second signal” can
broadly, but reasonably, be interpreted as representing first and second
instances of the same signal or the same signal at first and second points of
time (Ans. 10-11). In other words, Suzuki generates a first signal as an
interrupt request signal to the CPU to correct a first portion of program and,
at a later point in time, generates a second signal as an interrupt request
signal to correct a second portion of a program (Figs. 4A, 4B; col. 6, ll. 27-
36; col. 6, l. 65 to col. 7, l. 2).
In view of the above discussion, we find that the Examiner did not err
in concluding that all of the limitations of independent claim 64 are present
in the disclosure of Suzuki. Accordingly, the Examiner’s 35 U.S.C. § 102(b)
rejection of independent claim 64, as well as the rejection of dependent
claim 65 not separately argued by Appellants, is sustained.

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Claim 66
We also sustain the Examiner’s anticipation rejection, based on
Suzuki, of dependent claim 66 which adds the requirement of a second
coincidence detection circuit to the first detection circuit recited in claim 65
upon which claim 66 is dependent. We are not persuaded by Appellants’
argument that Suzuki discloses only a single coincidence detecting circuit,
i.e., PC comparison register section 20 of the ROM correction processing
circuit 24, in contrast to the claimed requirement of a second coincidence
circuit (App. Br. 13; Reply Br. 10-16).
Similar to our finding with respect to the Examiner’s rationale for
rejecting claim 64, we find no error in the Examiner’s line of reasoning
which determines that a number of instances of the ROM correction
processing circuit are created in correspondence to the number of portions of
the program module that are to be corrected (Ans. 11). As disclosed by
Suzuki, the PC value latch section 22, which is part of the PC comparison
register 24, is updated with the address of each of the portions of the
program module needing correction as the main program is run (Fig. 4A;
col. 6, ll. 6-11; col. 7, ll. 2-7). Further, while Appellants contend (Reply Br.
11) that Suzuki’s circuitry is incapable of simultaneously comparing two
bug addresses with a single program address, we find no such simultaneous
comparison requirement in claim 66.
Lastly, we note that, aside from arguments of counsel, Appellants
have set forth no evidence which would overcome the Examiner’s stated
position. See Estee Lauder Inc. v. L’Oreal, S.A., 129 F.3d 588, 595 (Fed.
Cir. 1997) (“[A]rguments of counsel cannot take the place of evidence
lacking in the record.”).
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Claims 67 and 68
The Examiner’s anticipation rejection of dependent claims 67 and 68,
based on Suzuki, is also sustained. Appellants contend the Examiner erred
in equating Suzuki’s stored number of correcting portions with the claimed
feature of counting the number of coincidences of bug addresses with
program addresses. According to Appellants (App. Br. 14-16; Reply Br. 17-
23), Suzuki’s stored number of correcting portions is a pre-set value that is
not based on the number of address coincidences. In a related argument,
Appellants contend (App. Br. 16-17: Reply Br. 24) that Suzuki’s disclosure
(col. 5, ll. 10-21) of a “number of use bytes” refers to the number of bytes of
each correction program, not the number of address coincidences of program
addresses and bug addresses.
We agree with the Examiner, however, that Appellants’ arguments
mischaracterize the Examiner’s stated position. As pointed out by the
Examiner (Ans. 12-13), the Examiner has not suggested that the number of
correcting portions in Suzuki, nor the number of use bytes, represents the
number of address coincidences. Instead, as explained by the Examiner
(Ans. 13), each time a bug address coincides with a program address in
Suzuki, the initial number of program portions to be corrected is
decremented (Fig. 4A, step S5; Fig. 4B, step S28). This decremented value,
when considered with the initial number of program portions to be corrected,
represents the number of times address coincidence has occurred as claimed.
Appellants’ further argument (Reply Br. 23) that Suzuki does not
disclose the generation of a count which represents the number of times a
ROM interruption request has been generated is also not persuasive. While
we find no support in Suzuki for Appellants’ conclusion, we note that the
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language of claim 67 and 68 requires only the counting of the number of
address coincidences, not the number of interruption requests.

Claim 69
We also sustain the Examiner’s anticipation rejection, based on
Suzuki, of dependent claim 69. Appellants’ arguments (App. Br. 18-19;
Reply Br. 25-26) are not persuasive of any error in the Examiner’s
determination (Ans. 13-14) that the particular correction portion of the
program module to be corrected in Suzuki is selected based on a value which
represents the number of times bug addresses and program addresses
coincide. As described by Suzuki, a decremented value representing the
number of program portions that have been corrected is used for setting the
ROM correction processing for the next program portion to be corrected
(col. 6, ll. 58-62).

35 U.S.C. § 103(a) REJECTION
We also sustain the Examiner’s obviousness rejection, based on the
combination of Suzuki with Miyazawa, of independent claim 63.
Appellants’ arguments do not challenge the Examiner’s application of
Miyazaki’s teaching of storing correction programs in random access
memory (RAM) to Suzuki (Ans. 5). Instead, Appellants’ arguments focus
on the contention that neither Suzuki nor Miyazawa discloses that a counter
is incremented when a program address coincides with a first or second bug
address (App. Br. 22-28; Reply Br. 28-35). In particular, Appellants point to
Suzuki’s disclosure that the stored number of program correcting portions is
decremented, not incremented as claimed (App. Br. 25).
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We find Appellants’ arguments unpersuasive of any error in the
Examiner’s stated position. As explained by the Examiner, incrementing
(counting up) and decrementing (counting down) are analogous operations
(Ans. 16). Further, as pointed out by the Examiner, Suzuki does disclose
(col. 9, ll. 52-54) that incrementing a counter is known, albeit for the
purpose of updating a position counter rather than a stored program
correction counter (id.).
We agree with the Examiner that the choice of incrementing a counter
rather than decrementing a counter to keep track of the number of program
portions corrected in Suzuki would have been obvious to the ordinarily
skilled artisan and would have yielded predictable results. When there are a
finite number of known identified, predictable solutions (e.g., counter
incrementing or counter decrementing), ordinarily skilled artisans would
have had a good reason to pursue the known options within their grasp,
including incrementing, rather than decrementing, the stored program
correction counter in Suzuki. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398, 421 (2007).

CONCLUSION
Based on the analysis above, we conclude that the Examiner did not
err in rejecting claims 64-69 for anticipation under 35 U.S.C. § 102(b), and
rejecting claim 63 for obviousness under 35 U.S.C. § 103(a).

DECISION
The Examiner’s decision rejecting claims 63-69 is affirmed.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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