Ex Parte Knowles et al

Patent Trial and Appeal Board

Jan 30, 2017

12205693 (P.T.A.B. Jan. 30, 2017)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/205,693 09/05/2008 Gareth J. Knowles 160.0020 7361
25534 7590 01/30/2017
CAHN & SAMUELS LLP
1100 17th STREET NW
SUITE 401
WASHINGTON, DC 20036
EXAMINER
SANDERS, STEPHEN
ART UNIT PAPER NUMBER
2434
MAIL DATE DELIVERY MODE
01/30/2017 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte GARETH J. KNOWLES and LINDSAY QUARRIE
_______________________

Appeal 2015-001860
Application 12/205,6931
Technology Center 2400
____________________

Before JEAN R. HOMERE, GARTH D. BAER, and
SHARON FENICK, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1–25, which constitute all of the
claims pending in this appeal. App. Br. 3. We have jurisdiction under 35
U.S.C. § 6(b).
We reverse.

1 Appellants identify the real party in interest as the inventors of record.
App. Br. 1. An oral hearing was held in this appeal on January 19, 2017.

Appeal 2015-001860
Application 12/205,693

2

Appellants’ Invention
Appellants invented an ASIC anti-tamper method and integrated laser
circuit for self-destroying a target semiconductor IC (200) containing a laser
diode array (110) and an IC component’s die wafer (130) to prevent reverse
engineering of the die wafer. Spec. ¶ 1, Fig. 2. In particular, upon receiving
from a sensor (350) a signal indicating unlawful tampering, a power supply
(360) energizes the laser diode array (110) to project focused laser energy
into the target semiconductor IC component (130), thereby damaging the
semiconductor IC (200). Id. ¶¶ 33, 38, Figs. 2, 3.

Illustrative Claim
Independent claim 1 is illustrative, and reads as follows:
1. An integrated circuit comprising:
at least one laser diode;
at least one target integrated circuit component;
said at least one laser diode disposed such that laser energy emitted by
said at least one laser diode is launched in the direction of said at least one
target integrated circuit component;
wherein upon receipt of a predetermined signal said at least one laser
diode energizes and projects focused laser energy into said target integrated
circuit component damaging said target integrated circuit component.

Prior Art Relied Upon
McCalley et al. 5,956,415 Sept. 21, 1999
Rosen et al. US 2005/0100077 A1 May 12, 2005
Appeal 2015-001860
Application 12/205,693

3
Yamazaki et al. US 2005/0110091 A1 May 26, 2005

Rejections on Appeal
Claims 1–21 stand rejected under 35 U.S.C. § 103(a) (pre-AIA) as
being unpatentable over the combination of Rosen and Yamazaki. Final Rej.
5–14.
Claims 22–25 stand rejected under 35 U.S.C. § 103(a) (pre-AIA) as
being unpatentable over the combination of McCalley, Yamazaki, and
Rosen. Final Rej. 14–17.

ANALYSIS
We consider Appellants’ arguments as they are presented in the
Appeal Brief, pages 10–26, and the Reply Brief, pages 1–3.
Regarding the rejection of claim 1, Appellants argue the proposed
combination of Rosen and Yamazaki does not teach or suggest, upon
receiving a predetermined signal, a laser diode energizes and projects
focused laser energy into a target IC component to thereby damage the IC
component. App. Br. 20–23; Reply Br. 2. In particular, Appellants argue
that Yamazaki discloses using an external laser to improve the fabrication
process by repairing (not causing or creating) damage to the IC component,
and thereby does not cure the noted deficiencies of Rosen. App. Br. 21–23.
This argument is persuasive.
At the outset, we note Yamazaki discloses oxidation treatment at high
temperature (700 degrees or higher) for a long duration of time is known to
cause damage to the substrate of an IC material, and impairs the throughput
thereof. Yamazaki ¶ 12. Further, Yamazaki discloses a laser fabrication
Appeal 2015-001860
Application 12/205,693

4
process that involves the use of a laser beam or intense irradiated light to
cure a silicon film damaged by an ion doping process. Id. at ¶ 74. Likewise,
Yamazaki discloses using the laser beam to recover the crystallinity of
damaged impurity doped regions. Id. at ¶¶ 66, 80. At best, Yamazaki
teaches causing damages to an IC component through a heating process, and
using an external laser beam to irradiate an IC component as a way to repair
the component from previously sustained damage. We therefore agree with
Appellants that the Examiner erred in finding the cited disclosures of
Yamazaki teach or suggest using a focused beam emanating from a laser
diode to cause damage to an IC semiconductor component. App. Br. 21–23;
Ans. 15 (citing Yamazaki ¶¶ 9, 12, 56–68, 71–77, 80, 83–92, 98, 106, 113).
Because Appellants have shown at least one reversible error in the
Examiner’s obviousness rejection, we need not reach Appellants’ remaining
arguments. Consequently, we reverse the Examiner’s rejection of claim 1,
as well as claims 2–25, which recite the disputed limitations discussed
above.
DECISION
We reverse the Examiner’s obviousness rejections under 35 U.S.C. §
103(a) of claims 1–25 as set forth above.

REVERSED