Ex Parte Knight et al

Patent Trial and Appeal BoardMar 27, 2017

12710616 (P.T.A.B. Mar. 27, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/710,616 02/23/2010 Richard Knight 42792-0382 9083 38881 7590 Infineon Technologies AG c/o Schiff Hardin LLP 666 Fifth Avenue Suite 1700 NEW YORK, NY 10103 03/29/2017 EXAMINER LINDLOF, JOHN M ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 03/29/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): lbrutman @ schiffhardin.com patents-NY @ schiffhardin.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte RICHARD KNIGHT, NEIL HAS TIE, SIMON BREWERTON, and GLENN FARRALL Appeal 2016-002518 Application 12/710,616 Technology Center 2100 Before JOSEPH L. DIXON, NATHAN A. ENGELS, and MATTHEW J. McNEILL, Administrative Patent Judges. DIXON, Administrative Patent Judge. DECISION ON APPEAL Appeal 2016-002518 Application 12/710,616 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims 1—26. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. The claims are directed to reading to and writing from peripherals with temporally separated redundant processor execution. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A method comprising: reading data by a first processor from a peripheral device, the peripheral device being peripheral to the first processor; copying the data to a register, the register being independent from the first processor and a second processor; inhibiting a read attempt of the peripheral device by the second processor; and reading the data from the register by the second processor. REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Passint et al. US 6,230,252 B1 May 8, 2001 Nguyen et al. US 2003/0005380 Al Jan. 2, 2003 Subramanyan et al., Power Efficient Redundant Execution for Chip Multiprocessors, Workshop on Dependable and Secure Nanocomputing (WDSN) (June 2009). 2 Appeal 2016-002518 Application 12/710,616 REJECTIONS The Examiner made the following rejections: Claims 1—9 and 26 stand rejected under 35 U.S.C. § 102(a) as being anticipated by Subramanyan. Claims 12—15 and 17 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Nguyen. Claim 10 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Subramanyan in view of Passint. Claims 11 and 20-25 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Subramanyan in view of Nguyen. Claims 16, 18, and 19 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Nguyen in view of Subramanyan. ANALYSIS With respect to independent claims 1,12, 20, and 23, Appellants set forth separate arguments for patentability. Therefore, we will address Appellants’ arguments in the order set forth in the Appeal Brief. We concur with the conclusions reached by the Examiner, and adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken (Final Act. 2—12), and (2) the reasons set forth by the Examiner in the Examiner’s Answer in response to Appellants’ Appeal Brief (Ans. 3—6). We highlight and amplify certain teachings and suggestions of the references, as well as certain ones of Appellants’ arguments as follows. Claims 1—9 and 26 With respect to claims 1—9 and 26, Appellants argue the claims together. Therefore, we select independent claim 1 as the representative 3 Appeal 2016-002518 Application 12/710,616 claim for the group and will address Appellants arguments thereto. 37 C.F.R. § 41.37(c)(l)(iv). Appellants contend that the Examiner has not established a prima facie case of anticipation under 35 U.S.C. § 102 because, according to Appellants, the Subramanyan reference does not disclose a register independent from the second processor. (App. Br. 3). Appellants specifically contend: The LVQ (cited as the “register” in the Final Office Action) is not independent from the R-core (cited as the “second processor” in the Final Office Action). In fact, Subramanyan explicitly states that the LVQ is a part of the R-core. During redundant processing, “loads from the P-core are transferred over the interconnect and stored in the LVQ structure in the R-core. (Subramanyan at page 2 (emphasis added).) This is the opposite of the structure recited by claim 1, which explicitly recites a “register being independent from ... a second processor. Therefore, Subramanyan does not disclose each and every element as set forth in the claim, and the rejection should be vacated. (App. Br. 4). Appellants further contend that the “Examiner has not established a prima facie case of anticipation under § 102(a) because Subramanyan does not disclose inhibiting a read attempt of the peripheral device by the second processor.” (App. Br. 4). Appellants further argue: The section of Subramanyan cited in the Final Office Action refers to allocation of redundant processing tasks between the R-core and P-core. The R-core and P-core are cited in the Final Office Action as purportedly disclosing the first processor and the second processor. As such, neither the P-core nor the R- core can be a peripheral device “being peripheral to the first processor.” The Final Office Action later asserts that the “data cache” is the peripheral device, and neither the cited language nor any other portion of Subramanyan teaches or suggests inhibiting the P-core or the R-core from reading from the data 4 Appeal 2016-002518 Application 12/710,616 cache, as would be necessary under the Examiner's interpretation of Subramanyan elsewhere in the Final Office Action to support the rejection. In fact, the cited section of Subramanyan does not actually teach or suggest “inhibiting a read attempt” in any way. As described in Subramanyan, “[t]he primary and secondary core execute the same instruction stream, with the same input data stream, but the P-core is temporally ‘ahead’ of the R-core, i.e., the R-core executes a particular instructions after it has been executed by the P-core.” (Subramanyan, p. 2.) To facilitate this, loads from the P-core are transferred over the interconnect and stored in the LVQ structure of the R-core. The instructions are always read twice, albeit at different times, once by each core of the processor. The instructions of Subramanyan are never “inhibited,” as recited by claim 1 in combination with the other elements of that claim. (App. Br. 5). Finally, Appellants contend that “the Examiner has not established aprima facie case of anticipation under§ 102(a) because Subramanyan does not disclose two processors.” (App. Br. 5—6). “In the patentability context, claims are to be given their broadest reasonable interpretations . . . limitations are not to be read into the claims from the specification.” In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (citations omitted). Any special meaning assigned to a term “must be sufficiently clear in the specification that any departure from common usage would be so understood by a person of experience in the field of the invention.” Multiform Desiccants, Inc. v. Medzam, Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998); see also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381 (Fed. Cir. 2008) (“A patentee may act as its own lexicographer and assign to a term a unique definition that is different from its ordinary and customary meaning; however, a patentee must clearly express that intent in the written 5 Appeal 2016-002518 Application 12/710,616 description.”). Absent an express intent to impart a novel meaning to a claim term, the words take on the ordinary and customary meanings attributed to them by those of ordinary skill in the art. Brookhill- Wilk 1, LLC v. Intuitive Surgical, Inc., 334 F.3d 1294, 1298 (Fed. Cir. 2003) (citation omitted). We disagree with Appellants contentions and find that the Examiner has clearly set forth the interpretation of the claims and explained how the prior art discloses the invention recited in the language of independent claim 1. (Ans. 3—5). The Examiner specifically maintains: It is noted that while Appellant has argued that “A processor, under the broadest reasonable interpretation, is not the same as a core . . .”, Appellant has not provided any explanation or definition of the “broadest reasonable interpretation” of a “processor” that cannot be taught by a core of Subramanyan. The P-core and identical un-augmented portion of the R-core carry out instructions of a computer program, therefore they are processors. (Ans. 5). Appellants set forth similar arguments in the Reply Brief. Appellants contend “[t]he P-core and the un[-]augmented portion of the R-core are identical. Independent claim 1 requires a first processor and a second processor. The Examiner cannot refer to the same processor as being two, separate claimed processors (the first and second processors).” (Reply Br. 2). Appellants further contend: Subramanyan discloses “Load instructions executing in the R-core do not access the data cache and instead obtain the load values from the LVQ.” See Subramanyan, page 2, last sentence. Subramanyan does not disclose the second processor attempting to read from the data cache, and this read being inhibited. Not accessing the data cache is not the same as inhibiting a read attempt, as required by independent claim 1. 6 Appeal 2016-002518 Application 12/710,616 (Reply Br. 2). We disagree with Appellants and find that Appellants have not identified any specific interpretation of the claimed “processor” or “inhibiting a read” with which to differentiate the claimed invention from the disclosure of the Subramanyan reference. Consequently, we find Appellants’ argument to be unpersuasive of error in the Examiner’s finding of anticipation, and we sustain the rejection of independent claim 1. Claims 12—15 and 17 With respect to independent claim 12—15 and 17, Appellants contend: The Examiner erred in concluding that the disclosure of Nguyen at paragraph 24 discloses logging the data write by the first processor. In fact, Nguyen does not disclose logging the data write from the first processor, nor does it disclose a logger device. The only thing Nguyen discloses storing, at paragraph 24, is the “comparison results," which are sent “to an accumulate register in cache 10.” The comparison results are not the same as the data writes themselves, produced by both the first processor and the second processor. Rather, the “comparison” is a True/False value used “to determine that the output of processing the test instruction set by each core is identical.” (Nguyen at 116.) (App. Br. 6). The Examiner maintains “[t]he results of Nguyen are logged and compared by core checking units (see e.g. para. [0024]). Test results are both written to a peripheral device and compared so that any discrepancies can be flagged (see e.g. para. [0018-9]).” (Ans. 5). Appellants further contend: Nguyen discloses “Arbitration/PRC units 24 and 26 are capable of comparing the results of cores 4 and 6.” See Nguyen, 7 Appeal 2016-002518 Application 12/710,616 paragraph [0024], Comparing the results of two cores is not the same as logging a data write by a logger device, as required by independent claim 12. (Reply Br. 2). Any special meaning assigned to a term “must be sufficiently clear in the specification that any departure from common usage would be so understood by a person of experience in the field of the invention.” Multiform Desiccants Inc., 133 F.3d at 1477; see also Helmsderfer, Inc., 527 F.3d at 1381 (“A patentee may act as its own lexicographer and assign to a term a unique definition that is different from its ordinary and customary meaning; however, a patentee must clearly express that intent in the written description.”). We disagree with Appellants’ argument and find Appellants’ argument does not show error in the Examiner’s factual findings or finding of anticipation. Appellants have not identified any express definition or claim interpretation with which to differentiate the logging and comparing as disclosed by the Nguyen reference. As a result, we sustain the rejection of independent claim 12 and dependent claims 13—15 and 17 not separately argued. Claim 10 With regards to dependent claim 10, Appellants do not set forth separate arguments for patentability. As a result, we sustain the rejection of dependent claim 10 for the same reasons as parent independent claim 1. Claims 11 and 20-25 Appellants recite the language of independent claim 20 and contend “[cjlaim 20 recites ‘a null response peripheral device configured to receive redirected data writes from the another of the at least two processors.’ This 8 Appeal 2016-002518 Application 12/710,616 is not taught or suggested by Subramanyan, Nguyen, or their combination.” (App. Br. 7). Appellants further contend: As an initial matter, none of claims 1, 2, or 11 recite “a null response peripheral device,” nor do any of claims 1, 2, or 11 recite “receiving redirected data writes.” Therefore, the Final Office Action is defective in that it does not even allege that the cited references teach every limitation of the claims. (App. Br. 7). The Examiner finds that Appellants are arguing the references individually rather than the combination as applied in the grounds of the rejection. The Examiner further maintains: Further, Subramanyan teaches or suggests a peripheral device configured to receive redirected data writes. During a load instruction in the P-core, data is loaded (read) as normal from the indicated memory address (in the data cache). In the R-core, the load (read) is not performed as normal from the indicated address, but is instead redirected to the LVQ. This is because data has been redirected to the LVQ peripheral device. (Ans. 5—6). Appellants further contend: Subramanyan discloses “Load instructions executing in the R- core do not access the data cache and instead obtain the load values from the LVQ.” See Subramanyan, page 2, last sentence. Not accessing the data cache is not the same as redirecting a data write, as required by independent claim 20. There is no indication that the R-core first attempts to access the data cache, and this access is redirected to the LVQ; moreover, an “access” is a read rat her [sic] than a write, as claimed. Again, Subramanyan does not disclose receive a redirected data write. (Reply Br. 2). We agree with the Examiner that Appellants’ arguments are directed to the references individually where the Examiner has relied upon the Nguyen reference to teach or suggests “logging write data from multiple 9 Appeal 2016-002518 Application 12/710,616 cores to a logger device in order to check for faults (see e.g. para. [0014], [0016]).” (Final Act. 9). Furthermore, Appellants’ have not identified any express definition or meaning of the “null response peripheral device” which differentiates from the “peripheral device” is relied upon by the Examiner. Consequently, Appellants’ argument does not show error in the Examiner’s factual findings or conclusion of obviousness. As a result, we sustain the rejection of representative independent claim 20 and dependent claims 21 and 22, not separately argued. With respect to claims 23—25 and the dependent claim 11, Appellants do not set forth separate arguments for patentability. Therefore, we group these claims as falling with representative independent claim 20. Claims 16, 18, and 19 With respect to claims 16, 18, and 19, Appellants do not set forth separate arguments for patentability. Therefore, we sustain the rejection of these claims because Appellants have not shown error in the Examiner’s factual findings or the conclusion of obviousness. CONCLUSIONS The Examiner did not err in rejecting claims 1—9, 12—15, 17, and 26 based upon anticipation under 35 U.S.C. § 102, and the Examiner did not err in rejecting claims 10, 11, 16, and 18—25 based upon obviousness under 35 U.S.C. § 103. DECISION For the above reasons, we sustain the Examiner’s rejections of claims 1—26 under 35 U.S.C. §§ 102 and 103. No time period for taking any 10 Appeal 2016-002518 Application 12/710,616 subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 11