Ex Parte Kisdarjono et al

Patent Trial and Appeal Board

Feb 6, 2014

12045286 (P.T.A.B. Feb. 6, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/045,286 03/10/2008 Hidayat Kisdarjono SLA2345 8998
55286 7590 02/07/2014
SHARP LABORATORIES OF AMERICA, INC.
C/O LAW OFFICE OF GERALD MALISZEWSKI
P.O. BOX 270829
SAN DIEGO, CA 92198-2829
EXAMINER
JOY, JEREMY J
ART UNIT PAPER NUMBER
2896
MAIL DATE DELIVERY MODE
02/07/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HIDAYAT KISDARJONO and APOSTOLOS T. VOUTSAS
__________

Appeal 2011-012268
Application 12/045,286
Technology Center 2800
____________

Before TERRY J. OWENS, GEORGE C. BEST, and
DONNA M. PRAISS, Administrative Patent Judges.

PRAISS, Administrative Patent Judge.

DECISION ON APPEAL

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Application 12/045,286

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Appellants appeal under 35 U.S.C. § 134 the final rejection of claims
1, 3-11, and 21. We have jurisdiction over the appeal pursuant to 35 U.S.C.
§ 6(b).
We AFFIRM.
Appellants’ invention is said to be directed to “a gate dielectric
structure that permits enhanced off current suppression in a top gate thin-
film transistor” (Spec. 1:7-8).
Claim 1 is illustrative (key limitations in dispute italicized):
1. A method for forming a bottom-contacted top gate thin film
transistor (TFT) with enhanced off current suppression, the method
comprising:
providing a substrate;
forming source and drain regions overlying the substrate, each
having a channel interface top surface;
forming a channel interposed between the source and drain,
with contact regions immediately overlying the source/drain (S/D)
interface top surfaces;
conformally depositing a first dielectric layer;
forming a second dielectric layer overlying the S/D interface
top surfaces, with an opening exposing a portion of the first dielectric
overlying the channel, as follows:
conformally depositing an etch stop layer overlying the
first dielectric layer;
conformally depositing the second dielectric overlying
the etch stop layer; and,
selectively etching the second dielectric overlying the
source-channel region; and,
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forming a gate overlying the second dielectric, etch stop, and
first dielectric layers covering the drain-channel contact region, and
the etch stop layer and the first dielectric layer covering the source-
channel contact region.
App. Br. 19 (Claims App’x).
Appellants appeal the rejection of claims 1, 3-6, 10, and 11 under
35 U.S.C. § 103(a) as being unpatentable over Miyasaka (US 5,811,323 A,
issued Sept. 22, 1998) in view of Takenaka (US 2004/0113214 A1,
published June 17, 2004) and Lin (US 2004/0072392 A1, published Apr. 15,
2004); the rejection of claims 7-9 under 35 U.S.C. § 103(a) as being
unpatentable over Miyasaka in view of Takenaka and Lin, and further in
view of Battersby (US 2004/0077133 A1, published Apr. 22, 2004); and the
rejection of claim 21 under 35 U.S.C. § 103(a) as being unpatentable over
Miyasaka in view of Takenaka.
Appellants argue the subject matter common to independent claims 1
and 21 (App. Br. 6-14). We select claim 1 as representative. Regarding the
remaining claims, Appellants rely on arguments made regarding claim 1 (id.
at 14-16). Accordingly, the rejection of claims 3-11 and 21 will stand or fall
with our analysis of the rejection of claim 1. 37 C.F.R. § 41.37(c)(1)(vii).

ISSUE
Did the Examiner reversibly err in determining that the combination
of Miyasaka’s method of forming a bottom-contacted top gate thin film
transistor with Takenaka’s second dielectric layer would have rendered
obvious the claimed steps of forming a second dielectric layer overlying the
S/D interface top surfaces, with an opening exposing a portion of the first
dielectric overlying the channel; and forming a gate overlying the second
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dielectric, etch stop, and first dielectric layers covering the drain-channel
contact region, and the etch stop layer and the first dielectric layer covering
the source-channel contact region? We decide this issue in the negative.

FINDINGS OF FACT AND ANALYSES
Appellants contend that the Examiner erred in rejecting claim 1
because:
Miyasaka does not disclose a gate that covers the drain-channel
contact region or the source-channel contact region, as recited in
claim 1. As defined in the claimed invention, the drain-channel
contact region is the top surface of the drain covered by the channel.

App. Br. 7. Appellants further assert that neither Takenaka nor Lin cure the
alleged deficiency of Miyasaka. Id. at 9.
Appellants additionally argue that the Examiner erred in combining
the process of Miyasaka with the process of Takenaka because “it is unlikely
that a practitioner would combine self-aligned and non-self-aligned
processes” as disclosed in the references. Id. at 11. Appellants assert that
Miyasaka discloses a low temperature, non-self-aligned process; Takenaka
discloses a high-temperature, self-aligned process wherein the source and
drain are doped after the formation of the gate; and Lin also discloses a self-
aligned process. Id. at 7-9.
The Examiner responds that
the appellants do not specifically claim that the gate covers the drain-
channel contact region and the source-channel contact region but
rather claim that [the] gate overlies the second dielectric, etch stop,
and first dielectric layers which those three layers in turn cover the
drain-contact region and that the gate also overlies the etch stop layer

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and the first dielectric layer which those two layers in turn cover the
source-channel contact region.
Ans. 13. The Examiner further responds that
Since[] Takenaka is only relied upon to teach forming a second
dielectric layer as claimed and modifying Miyasaka to include the
second dielectric layer as claimed, the examiner believes the
applicant’s arguments with regards using different processes to form
the source, drain and channel regions are without merit as only
Miyasaka [is] relied upon to teach the source, drain and channel as
claimed.

Id. at 14-15. The Examiner determines that one skilled in the art would have
been motivated to provide this second dielectric layer because Takenaka
teaches that providing a second dielectric layer wherein the total dielectric
layer thickness is greater over the drain contact area would enhance both ON
and OFF current characteristics. Id. at 15.
In the Reply Brief, Appellants assert that if vertical lines are drawn
from the edges of the gates shown in Figure 1E of Miyasaka and Figures 1D
and 3F of Takenaka, the vertical lines would fail to intersect the top surface
of the drain or source. Reply Br. 2. Appellants further argue that although
Takenaka teaches a second dielectric layer, claim 1 recites steps of forming a
second dielectric layer that are different from Takenaka’s method: “Claim 1
recites that the second dielectric layer is conformally deposited and then
selectively etched. In contrast, Takenaka forms a mask 401 (Fig. 3B) and
then forms layer 452 around the mask (Fig. 3C).” Id. at 3.
The preponderance of the evidence favors the Examiner’s obviousness
conclusion. We adopt the Examiner’s analysis on pages 3-5 and 13-17 of
the Answer as our own. We add the following discussion primarily for
emphasis.
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We begin, as we must, with the language of claim 1. The words of the
claim must be given their plain meaning unless the plain meaning is
inconsistent with the Specification. In re Zletz, 893 F.2d 319, 321 (Fed. Cir.
1989). Ordinary, simple English words whose meaning is clear and
unquestionable are to be construed to mean exactly what they say--absent, of
course, any indication that their use in a particular context changes their
meaning. Chef Am., Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372 (Fed.
Cir. 2004). During examination of a patent application, pending claims are
given their broadest reasonable construction consistent with the
Specification. In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed.
Cir. 2004). “[A]s applicants may amend claims to narrow their scope, a
broad construction during prosecution creates no unfairness to the applicant
or patentee.” In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed.
Cir. 2007).
We agree with the Examiner that the broadest reasonable
interpretation of claim 1 does not require forming the gate such that the gate
has a particular configuration other than to lie over or above the second
dielectric, etch stop, and first dielectric layers, which layers, in turn, are
recited as “covering the drain-channel contact region”; and to lie over or
above the etch stop layer and first dielectric layer, which layers, in turn, are
recited as “covering the source-channel contact region.” Claim 1 recites that
these layers are “covering” the drain-channel or source-channel contact
regions; claim 1 does not recite that the gate is covering the contact regions.
Claim 1 also does not recite “edges” of the gate, nor require any specific
location of gate edges.
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Claim 1 also does not require the gate to have any particular
relationship to the “interface top surfaces” recited therein, because those
specific words are used only with respect to “forming a channel” rather than
with respect to “forming a gate.” We understand the recited term “gate” to
be distinct from the recited term “channel” and that a channel may be
formed from material that is the same or different than the source and drain
regions. See Spec. 5:7 (referring to “channel 210” and “gate 220”); id. at
5:22-6:3; see also id. at 1:14-16 (“the channel is formed from a thin-film
material that is interposed between the source and drain, while overlapping
the regions (contact regions) of the source and drain.”).
Appellants’ position that “the drain-contact region is the top surface of
the drain covered by the channel” because it is “defined in the claimed
invention” (App. Br. 7) is not supported by either claim 1 or the
Specification. Claim 1 separately uses the terms “S/D interface top
surfaces” and “drain-channel contact region” and “source-channel contact
region” within the claim itself indicating these terms are distinct and not
interchangeable. The Specification indicates that it is not the top surface of
the S/D interface that is critical to the invention, but rather the area overlying
the drain channel interface depicted as a rectangle bounded by dashed lines
in Figure 5. Spec. 7:25-8:9. The Specification further indicates that the
shape of the gate is not critical when it states that the processes depicted in
the figures which form an asymmetric gate are equivalent to processes that
“form a symmetric gate.” Id. at 8:12-15.
Appellants do not dispute the teachings of Miyasaka, Takenaka, and
Lin. See generally App. Br.; see generally Reply Br. Miyasaka discloses
forming a first dielectric layer that covers the drain-channel contact region
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and the source-channel contact regions, and then forming a gate overlying
the first dielectric layer. Ans. 3-4. In the combination of Miyasaka with
Takenaka and Lin, the gate is formed overlying the second dielectric, etch
stop, and first dielectric layers as well as the etch stop layer and first
dielectric layer as recited in the claim. The broadest reasonable
interpretation of claim 1 thus encompasses the combination of Miyasaka
with Takenaka and Lin.
The Examiner’s rationale for modifying the method of Miyasaka with
the addition of a second dielectric is reasonable and supported by
Takenaka’s teaching that a second dielectric layer over the drain-channel
contact region contributes the advantage of enhancing ON-OFF current
characteristics. Id. at 4-5. Appellants’ argument that the process taught by
Takenaka would prevent one in the art from recognizing the suggestion of
Takenaka to provide an additional dielectric layer over the drain region is
not persuasive. It is not necessary that the inventions of the references be
physically combinable to render obvious the claimed invention. In re Sneed,
710 F.2d 1544, 1550 (Fed. Cir. 1983). One skilled in the art is not limited to
techniques used by Takenaka alone for a particular way of forming a second
dielectric layer in the Miyasaka method, as Miyasaka already discloses a
process including conformally depositing a dielectric layer. See Ans. 4.
Appellants correctly point out that Takenaka does not teach etching
the second dielectric layer, but rather teaches forming the second dielectric
layer around a mask. Reply Br. 3. Appellants’ argument is not persuasive,
however, because the Examiner relies upon Lin for teaching that the claimed
method of providing a second layer with an opening was known in the art.
Lin teaches conformally depositing a first layer, conformally depositing an
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etch stop layer, conformally depositing a second layer, and then selectively
etching the second layer as recited in claim 1. Ans. 5. (Independent claim
21 does not recite an etch stop layer or etching.) Appellants do not dispute
the Examiner’s finding that Lin teaches this method of providing a second
layer with an opening over a first layer.
On this record, we affirm the Examiner’s § 103 rejections.

DECISION
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136.

ORDER
AFFIRMED

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