Ex Parte Kim et al

Patent Trial and Appeal BoardAug 14, 2014

11198596 (P.T.A.B. Aug. 14, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/198,596 08/04/2005 Si-Hong Kim 51876P894 9504 8791 7590 08/15/2014 BLAKELY SOKOLOFF TAYLOR & ZAFMAN 1279 Oakmead Parkway Sunnyvale, CA 94085-4040 EXAMINER CHENG, DIANA ART UNIT PAPER NUMBER 2842 MAIL DATE DELIVERY MODE 08/15/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte SI-HONG KIM and SANG-SIC YOON ____________ Appeal 2012-003901 Application 11/198,596 Technology Center 2800 ____________ Before CHARLES F. WARREN, PETER F. KRATZ, and JEFFREY T. SMITH, Administrative Patent Judges. KRATZ, Administrative Patent Judge. DECISION ON APPEAL This is a decision on an appeal under 35 U.S.C. § 134 from the Examiner’s final rejection of claims 1, 5-8, 10, 12, and 14-17.1 We have jurisdiction pursuant to 35 U.S.C. § 6. Appellants’ claimed invention is directed to an apparatus and a method for controlling latency in a synchronous semiconductor device. For instance and according to Appellants, CAS latency “means a period until a valid data is outputted in response to a read instruction after the read instruction is inputted to the synchronous semiconductor memory device” 1 Cancelled claim 9 is inadvertently listed among the pending rejected claims (App. Br. 3). Appeal 2012-003901 Application 11/198,596 2 (Spec. 2, ll. 9-12). A “unit of the CAS latency is one cycle of external clock signal” (Spec. 2, ll. 12-14). Claim 1 is illustrative and reproduced below: 1. An apparatus for controlling a latency in a synchronous semiconductor device, comprising: a first counting block configured to count a cycle of a first clock signal output from a delay locked loop to generate a first binary code corresponding to a first counted cycle number; a delay block configured to delay the first clock signal by a predetermined delay amount and to generate a second clock signal; a second counting block configured to receive and count a cycle of the second clock signal to thereby generate a second binary code corresponding to a second counted cycle number; and a code comparison block configured to directly receive the first binary code from the first counting block, the second binary code from the second counting block and a read command signal and to compare the first binary code with the second binary code in response to the read command signal to thereby generate a latency control signal used in the synchronous semiconductor device, wherein a phase of the first clock signal leads a phase of an external clock signal by a first period; and a phase of the second clock signal lags the phase of the external clock signal by a second period, and wherein the predetermined delay amount adds the first period and the second period, wherein the latency control signal is activated to a logic high level when the first binary code is identical to the second binary code. wherein the first counting block and the second counting block are respectively set to a predetermined value based on a CAS latency before the first and the second clock signals are respectively inputted to the first and the second counting blocks. Appeal 2012-003901 Application 11/198,596 3 The Examiner relies on the following prior art references as evidence in rejecting the appealed claims: Osugi et al. US 3,641,561 Feb. 8, 1972 Kawamoto et al. US 3,449,726 Jun. 10, 1969 Dieffenderfer et al. US 2006/0048011 A1 Mar. 2, 2006 Hsu et al. US 6,580,287 B2 Jun. 17, 2003 Jiguet et al US 2005/0040862 A1 Feb. 24, 2005 The Examiner maintains the following grounds of rejection: Claims 1, 5, 10, 12, 14, and 17 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Osugi in view of Kawamoto and Dieffenderfer.2 Claim 6 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Osugi in view of Kawamoto, Dieffenderfer, and Hsu. Claims 7 and 8 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Osugi in view of Kawamoto, Dieffenderfer, Hsu, and Jiguet. Claims 15 and 16 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Osugi in view of Kawamoto, Dieffenderfer, and Jiguet. We agree with the Appellants that the Examiner’s rejections are not sustainable. Our reasons follow. “[T]he examiner bears the initial burden, on review of the prior art or on any other ground, of presenting a prima facie case of unpatentability.” In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). The Supreme Court of the United States explained that “a patent composed of several elements is not proved obvious merely by demonstrating that each of its elements was, independently, known in the prior art.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The 2 The Examiner inadvertently lists cancelled claim 9 among the rejected claims (Ans. 5). Appeal 2012-003901 Application 11/198,596 4 Supreme Court cautioned about adhering to “[r]igid preventative rules that deny factfinders recourse to common sense,” but stated that the “factfinder should be aware . . . of the distortion caused by hindsight bias and must be cautious of arguments reliant upon ex post reasoning.” Id. at 421. Rejected independent claims 1, 10 and 17 are drawn to apparatus or a method for controlling latency in a synchronous semiconductor device utilizing a latency control signal generated in a code comparison block wherein first and second binary codes generated in first and second counting blocks are compared, and wherein the counting blocks are respectively set/configured to predetermined values based on CAS latency before first and second clock signals, respectively, are inputted to the counting blocks for such binary code generation via counting a cycle of first and second clock signals, respectively. In Appellants’ claimed apparatus, a delay block is provided, which delay block is configured to delay the first clock signal by a predetermined delay amount and to generate the second clock signal and the code comparison block is configured to receive a read command signal that implements the comparison of the first and second binary codes generated in first and second counting blocks. In the first stated rejection, the Examiner maintains that Osugi teaches a first counting block (counter circuit 53) and a second counting block (decremental counter 54), each configured to receive and count a cycle of a clock signal received from element 52 which are arranged to generate a first and a second binary code, respectively, which codes are received by a code comparison block and are compared and generate a latency control signal in response to a read command signal received by the code comparison block, Appeal 2012-003901 Application 11/198,596 5 and wherein a phase of a first clock signal leads a phase of an external clock signal and a phase of the second clock signal lags the phase of the external clock signal, and wherein the latency control signal is activated to a logic high level when the first and second binary code signals are identical to each other (Ans. 5, 6; Osugi, col. 1, ll. 50-55, col. 2, ll. 9-38, Fig. 2, elements 51, 53, 54, 55). Moreover, the Examiner contends that the first and second counting blocks (incremental and decremental counter circuits 53 and 54) of Osugi are configured/set to a predetermined latency based on a CAS latency before first and second clock signals are inputted and such that the these counting blocks are set to two different predetermined clock cycle values (Ans. 6: Osugi, col. 1, l. 74- col. 2, l. 8, Figs. 3(b), 3(d)). However, the Examiner does not satisfactorily explain how the cited portions of Osugi, which are directed to the operation of a display system shift register 51, counter 53, decremental counter 54, and clock pulse generator 52, describe setting each of the counters 53 and 54 to a predetermined value based on a CAS latency before first and second clock signals are inputted, respectively, thereto. The Examiner turns to Kawamoto for a teaching of a buffer operatively located between a register and a display device, which buffer is asserted to act as a delay block and to store received output (Ans. 7, Kawamoto, col. 1, ll. 22-37, Fig. 1). The Examiner maintains that it would have been obvious to one of ordinary skill in the art to insert Kawamoto’s delay block in the system of Osugi at a location before the second counting block in order to store the output received in a manner such that the first clock signal is delayed by a predetermined amount so as to generate a second clock signal (Ans. 7). Appeal 2012-003901 Application 11/198,596 6 In addition, the Examiner takes the position that one of ordinary skill in the art would have been led to employ the teachings of Dieffenderfer respecting generating enable and disable signals with a register in combination with the register as taught by Osugi and Kawamoto for identifying events occurring during program execution (Ans. 7; Dieffenderfer, 1 ¶ 0008, Fig. 4). However, and as argued by Appellants, the Examiner has not persuasively articulated: (a) how and why one of ordinary skill in the art would have been led to modify the serial-type desk top computer display system of Osugi for indicating information stored in a recirculating shift register sequentially based on the teachings of Kawamoto respecting a buffer associated with a number display system, which latter system is arranged to avoid the display of futile or insignificant numbers by detecting whether the content stored in a buffer is zero or whether there is a decimal in a number to be displayed , and/or (b) why one of ordinary skill in the art would have been directed to further modify Osugi based on the disparate teachings of Dieffenderfer concerning a debug control register utilized in the real-time monitoring of software running on a microprocessor system, in a manner so as to result in an apparatus and/or a method for controlling latency in a semiconductor device corresponding to any of the rejected claims (App. Br. 6-15; Reply Br. 3-8; Osugi, abstract; Kawamoto, col. 2, ll. 45-49; Dieffenderfer, abstract). See In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) ("[R]ejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of Appeal 2012-003901 Application 11/198,596 7 obviousness"), cited with approval in KSR Int'l. Co. v. Teleflex Inc., 550 U.S. at 417-18. In this regard and for the reasons argued by Appellants, the Examiner has not persuasively articulated how the applied display system of Osugi, the applied number display system teachings of Kawamoto, and/or the applied microprocessor real time monitoring teachings of Dieffenderfer alone or, in combination, teach or suggest an apparatus or method controlling latency in a synchronous semiconductor device, as claimed. After all, rejections based on §103(a) must rest on a factual basis with these facts being interpreted without hindsight reconstruction of the invention from the prior art. See In re Warner, 379 F.2d 1011, 1017 (CCPA 1967). The Examiner has not established that the additional references applied with respect to certain dependent claims cures the deficiencies of the base rejection upon which they are built. On this record, we reverse the stated obviousness rejections. CONCLUSION The Examiner’s decision to reject the appealed claims is reversed. REVERSED lp