Ex Parte Kilzer et al

Patent Trial and Appeal Board

Mar 21, 2017

13450079 (P.T.A.B. Mar. 21, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/450,079 04/18/2012 Kevin Lee Kilzer 68354.118706 6994
86528 7590 03/23/2017
Slay den Grubert Beard PLLC
401 Congress Avenue
Suite 1900
Austin, TX 78701
EXAMINER
PARK, ILWOO
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
03/23/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
trosson @ sgbfirm.com
patent @ sgbfirm. com
dallen @ sgbfirm. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KEVIN LEE KILZER, SEAN STEEDMAN,
JERROLD S. ZDENEK, VIVIEN N. DELPORT,
ZEKE LUNDSTRUM, and FANIE DUVENHAGE
Appeal 2016-007453
Application 13/450,0791
Technology Center 2100
Before DEBRA K. STEPHENS, BRADLEY W. BAUMEISTER, and
MICHAEL J. ENGLE, Administrative Patent Judges.
ENGLE, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1, 2, and 5—32, which are all of the claims pending in the application.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Technology
The application relates to “a logic device for combining various
interrupt sources into a single interrupt source.” Spec. Title (caps omitted).
1 According to Appellants, the real party in interest is Microchip Technology
Inc. App. Br. 2.
Appeal 2016-007453
Application 13/450,079
Illustrative Claim
Claim 1 is illustrative and reproduced below.
1. A processor, comprising:
a RISC CPU core;
a plurality of peripherals generating a plurality of digital
output signals;
a configurable logic cell peripheral;
wherein the configurable logic cell peripheral comprises a
signal selector configured to select a set of input signals from a
plurality of input signals, wherein the plurality of input signals
are provided by at least said digital output signals, and at least
one configurable logic cell which can be configured to perform
a logic function, wherein the programmable logic function
combines the set of input signals into a single digital output
signal,
wherein the single digital output signal controls a drive
strength or a slew rate at an output port which receive data
directly from the RISC CPU.
Rejections
Claims 1, 2, 5, 11—15, 31, and 32 stand rejected under 35 U.S.C.
§ 103(a) as obvious over the combination of Brophy (US 6,637,017 Bl;
Oct. 21, 2003) and Fletcher (US 2007/0271060 Al; Nov. 22, 2007). Final
Act. 2.
Claims 6—9 and 16—19 stand rejected under 35 U.S.C. § 103(a) as
obvious over the combination of Brophy, Fletcher, and Rupp
(US 7,062,520 B2; June 13, 2006). Final Act. 9.
Claims 10 and 20—26 stand rejected under 35 U.S.C. § 103(a) as
obvious over the combination of Brophy, Fletcher, and Yang et al.
(US 2009/0113169 Al; Apr. 30, 2009). Final Act. 10-11.
Claims 27—30 stand rejected under 35 U.S.C. § 103(a) as obvious over
the combination of Brophy, Fletcher, Yang, and Rupp. Final Act. 15.
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Appeal 2016-007453
Application 13/450,079
ISSUES
1. Did the Examiner err in finding the combination of Fletcher and
Brophy teaches or suggests “a RISC CPU core,” as recited in claim 1?
2. Did the Examiner err in finding the combination of Fletcher and
Brophy teaches or suggests “a configurable logic cell peripheral. . .
comprises ... a configurable logic cell,” as recited in claim 1?
3. Did the Examiner err in combining Fletcher and Brophy for
purposes of claim 1?
CONTENTIONS AND ANALYSIS
Claim 1 recites a processor comprising “a RISC CPU core” and “a
configurable logic cell peripheral.” The Examiner relies on a combination
of Fletcher and Brophy for teaching these limitations.
Appellants contend Brophy’s state machine or macro cell fails to
teach a central processing unit (CPU). App. Br. 7—8; Reply Br. 3. However,
the Examiner relies on Fletcher for teaching the claimed CPU, not Brophy.
Final Act. 4 (“Brophy does not teach, however Fletcher teaches the device
being a processor comprising a RISC CPU core . . .”); Fletcher 126.
Appellants further contend Fletcher fails to teach a “configurable
logic device.” App. Br. 6—7; Reply Br. 4. However, the Examiner relies on
Brophy for teaching a configurable logic cell peripheral comprising a
configurable logic cell, not Fletcher. Final Act. 3 (citing Brophy 2:33—35,
Fig. 1).
“Non-obviousness cannot be established by attacking references
individually where the rejection is based upon the teachings of a
combination of references.” In re Merck & Co., 800 F.2d 1091, 1097 (Fed.
Cir. 1986). Thus, we are not persuaded by Appellants’ arguments that one
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Application 13/450,079
reference fails to teach a limitation when the Examiner relies on a second
reference for that limitation.
Appellants also contend “[a] person skilled in the art would not be
encouraged to combine the teachings of Brophy and Fletcher” and “there is
no nexus between Brophy and Fletcher” because “Brophy teaches a PLD
[i.e., programmable logic device] while Fletcher at best teaches that the
entire system . . . can be formed by a field programmable gate array
[FPGA].” App. Br. 8.
The Examiner lists the similarities of the two references, and finds
that adding Fletcher’s RISC CPU “would increase versatility in processing”
compared to “a simple state machine of Brophy.” Ans. 18,22. “Therefore,
it would have been obvious to one of ordinary skill in the art at the time of
the invention to modify to implement Fletcher’s teaching above including
the device having a RISC CPU core in order to increase functionality of the
device rather than the state machine of Brophy.” Final Act. 4.
Appellants have not sufficiently addressed the Examiner’s findings.
For example, even if Brophy taught a PFD and Fletcher taught an FPGA
with a RISC CPU core (see Fletcher 126), Appellants have not persuaded us
of error in the Examiner’s finding that adding a RISC CPU core to Brophy
would increase versatility and functionality beyond Brophy’s simple state
machine. Nor have Appellants sufficiently explained why such a
substitution would be uniquely challenging or difficult to a person of
ordinary skill in the art or yield anything more than a predictable result. As
the Supreme Court has said, “when a patent simply arranges old elements
with each performing the same function it had been known to perform and
yields no more than one would expect from such an arrangement, the
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Application 13/450,079
combination is obvious.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417
(2007) (quotation omitted). “It is not the function of this court to examine
the claims in greater detail than argued by an appellant, looking for
[patentable] distinctions over the prior art.” In re Baxter Travenol Labs.,
952 F.2d 388, 391 (Fed. Cir. 1991).
For claims 21—30, Appellants contend “Yang does not fill the gaps”
but otherwise rely on the “same arguments” as claim 1 (App. Br. 9), which
are not persuasive for the reasons discussed above.
Accordingly, we sustain the Examiner’s rejection of claim 1, as well
as claims 2 and 5—32, which Appellants argue are patentable for similar
reasons. See App. Br. 8—9; 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
For the reasons above, we affirm the Examiner’s decision rejecting
claims 1,2, and 5—32.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
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