Ex Parte Kawae et al

Patent Trial and Appeal Board

Sep 15, 2014

12504897 (P.T.A.B. Sep. 15, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/504,897 07/17/2009 Daisuke KAWAE 740756-3323 1017
22204 7590 09/15/2014
NIXON PEABODY, LLP
401 9TH STREET, NW
SUITE 900
WASHINGTON, DC 20004-2128
EXAMINER
SUN, YU-HSI DAVID
ART UNIT PAPER NUMBER
2895
MAIL DATE DELIVERY MODE
09/15/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte DAISUKE KAWAE, YOSHIYUKI KUROKAWA,
and HIDEKAZU MIYAIRI
________________

Appeal 2012-012187
Application 12/504,897
Technology Center 2800
________________

Before, ADRIENE LEPIANE HANLON, BEVERLY A. FRANKLIN, and
KAREN M. HASTINGS, Administrative Patent Judges.

HASTINGS, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE

The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 5 and 7-13 under 35 U.S.C. §103(a) as being
unpatentable over Akimoto (US PG Pub 2007/0072439 A1, pub. Mar. 29,
2007) in view of Yamazaki (US PG Pub 2006/0027804 A1, pub. Feb. 9,
2006) and Miyairi (US 6,803,296 B2, issued Oct. 12, 2004). An oral hearing
was held on September 9, 2014. We have jurisdiction under
35 U.S.C. § 6(b).

Appeal 2012-012187
Application 12/504,897

2

Claim 5 is illustrative of the claimed subject matter:
5. A semiconductor device comprising:
a first gate electrode layer over a substrate;
a first gate insulating layer over the first gate electrode
layer;
a conductive layer over and in contact with the first gate
insulating layer, the conductive layer overlapping the first gate
electrode layer;
a semiconductor layer over the conductive layer and the
first gate insulating layer;
a source electrode layer over the semiconductor layer, the
source electrode layer overlapping a first portion of the first
gate electrode layer;
a drain electrode layer over the semiconductor layer, the
drain electrode layer overlapping a second portion of the first
gate electrode layer;
a second gate insulting layer over the semiconductor
layer; and
a second gate electrode layer over the second gate
insulating layer, the second gate electrode layer overlapping a
third portion of the first gate electrode layer between the first
portion and the second portion,
wherein the semiconductor layer is in contact with the
first gate insulating layer over the third portion of the first gate
electrode layer.

Independent claim 10 is directed to a similar semiconductor device as
claim 5 (Claims App’x).
OPINION
We reverse the rejection.
The Examiner bears the initial burden of presenting a prima facie case
of obviousness. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). To
establish a prima facie case of obviousness, the examiner must show that
Appeal 2012-012187
Application 12/504,897

3
each and every limitation of the claim is described or suggested by the prior
art or would have been obvious based on the knowledge of those of ordinary
skill in the art. In re Fine, 837 F.2d 1071, 1074 (Fed. Cir. 1988).
We need to address only the independent claims (claims 5 and 10).
Those claims each require various insulating, semiconductor, conductive and
electrode layers in a specified configuration.
The Examiner admits that Akimoto fails to disclose the required first
and second conductive layers, as well as the semiconductor layer and relies
upon Yamazaki for these layers (Answer 3, 10). The Examiner relies
explicitly on layers 149a and 149b as the first and second conductive layers,
and 151a and 151b as the claimed semiconductor layer (id.).
However, as pointed out by Appellants, Yamazaki describes all of
these layers (i.e., 149a, 149b, 151a, and 151b) as semiconductor layers (e.g.,
Yamazaki para. [0378]; App. Br. 5). The Examiner’s position is that, since
Appellants’ conductive layer is a doped semiconductor layer, any doped
semiconductor layer may be either labeled as a conductive layer or a
semiconductor layer (Answer 7). Appellants’ position is that the Examiner
may not arbitrarily pick some semiconductor layers of Yamazaki and label
them as conductive layer and label other layers as a semiconductor layer in
order to meet all the required claim limitations (App. Br. 5; Reply Br. 3).
We agree with Appellants, since within the context of the claimed invention,
a “conductive” layer must at least be more conductive than a
“semiconductor” layer. See In re Am. Acad. of Sci. Tech Ctr., 367 F.3d
1359, 1364 (Fed. Cir. 2004) (The scope of the claims in patent applications
is not determined solely on the basis of the claim language, but upon giving
claims their broadest reasonable construction in light of the specification as
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Application 12/504,897

4
it would be interpreted by one of ordinary skill in the art.). On this record
the Examiner has not established that it is reasonable to label Yamazaki’s
semiconductor layers 149a and 149b as a “conductive” layer relative to
Yamazaki’s semiconductor layers 151a and 151b, and then modify Akimoto
(with Miyairi) so as to result in the claimed subject matter.
Thus, a preponderance of the evidence supports Appellants’ position
that the Examiner has not established that the combined prior art achieves
the claimed semiconductor device with its specified configuration of layers.
On the record before us, the Examiner has not shown that each and
every limitation of the claim is either described or suggested by the prior art
or would have been obvious based on the knowledge of the ordinary artisan.
See In re Fine, 837 F.2d at 1074; see also In re Warner, 379 F.2d 1011,
1017 (CCPA 1967) (“A rejection based on section 103 clearly must rest on a
factual basis, and these facts must be interpreted without hindsight
reconstruction of the invention from the prior art”). The fact finder must be
aware “of the distortion caused by hindsight bias and must be cautious of
arguments reliant upon ex post reasoning.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 421 (2007) (citing Graham v. John Deere Co., 383 U.S. 1, 36
(1966) (warning against a “temptation to read into the prior art the teachings
of the invention in issue”)).
Accordingly, we reverse the rejection.
DECISION/ORDER

It is ordered that the Examiner’s decision is reversed.
REVERSED
cam