Ex Parte Joshua et alDownload PDFPatent Trial and Appeal BoardMay 25, 201714161423 (P.T.A.B. May. 25, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/161,423 01/22/2014 Eitan Joshua MP5165D4 / MV1-0444USC4 8418 11280 7590 05/30/2017 T ee Rr Haves; r>lle EXAMINER 601 West Riverside Ave., Suite 1400 Spokane, WA 99201 CHOI, CHARLES J ART UNIT PAPER NUMBER 2133 NOTIFICATION DATE DELIVERY MODE 05/30/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): lhpto@leehayes.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte EITAN JOSHUA, AMIT SHMILOVICH, MOSHE RAZ, SHAUL CHAPMAN, and EREZ AMIT Appeal 2016-007867 Application 14/161,4231 Technology Center 2100 Before ST. JOHN COURTENAY III, NORMAN H. BEAMER, and JOYCE CRAIG, Administrative Patent Judges. CRAIG, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1, 2, 4—6, 8—13, 16, and 18—20, which are all of the claims pending in this application. Claims 3, 7, 14, 15, and 17 are canceled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 According to Appellants, the real party in interest is Marvell World Trade Ltd. App. Br. 2. Appeal 2016-007867 Application 14/161,423 INVENTION Appellants’ application relates to the architecture of a multi-processor system. Spec. 12. Claim 1 is illustrative of the appealed subject matter and reads as follows: 1. A system comprising: a memory; and a memory interface module coupled to the memory, the memory interface module configured to control access to the memory, the memory interface module comprising a request combination module configured to: receive a memory read access request to access data stored in the memory, the memory read access request having a first priority; receive a pre-fetch request to pre-fetch data stored in the memory, the pre-fetch request having a second priority that is lower than the first priority; combine the memory read access request and the pre-fetch request to generate a combined memory access request, the combined memory access request being assigned the first priority associated with the memory read request; and based on (i) the combined memory access request and (ii) the first priority associated with the combined memory access request, access the memory to read data from the memory. REJECTIONS Claims 1, 2, 4—6, 8, 9, 12, 13, 16, 18, and 19 stand rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Conte (US 2010/0299481 Al; publ. Nov. 25, 2010), Goldberg (US 2010/0161558 Al; publ. June 24, 2010), and Hikichi (US 2012/0260056; publ. Oct. 11, 2012). Claim 10 stands rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Conte, Goldberg, Hikichi, and Minami (US 2012/0151152 Al; publ. June 14, 2012). 2 Appeal 2016-007867 Application 14/161,423 ANALYSIS In rejecting claim 1, the Examiner found that Conte teaches or suggests all of the recited limitations, except “receive a pre-fetch request to pre-fetch data stored in the memory, the pre-fetch request having a second priority that is lower than the first priority,” for which the Examiner relied on Hikichi, and “the combined memory access request being assigned the first priority associated with the memory read request,” for which the Examiner relied on Goldberg. Final Act. 2-4. Appellants contend the Examiner erred because the cited portions of Goldberg do not teach “the memory read access request having a first priority,” “the pre-fetch request having a second priority that is lower than the first priority,” and “the combined memory access request being assigned the first priority associated with the memory read request,” as recited in claim 1. App. Br. 5. Appellants argue that Goldberg teaches merging data object instances, not memory read requests or pre-fetch requests, as claim 1 requires. Id. Appellants also argue Goldberg teaches that a value having a lower priority is overwritten with values having a higher priority, while claim 1 requires combining the memory read access request and the pre fetch request to generate a combined memory access request. Id. at 6. Appellants further argue that nothing in Conte or Goldberg shows or suggests assigning a priority to the combined memory access request, where the combined memory access request is a combination of two requests. Id. Appellants’ arguments do not persuade us of Examiner error. Appellants attack the prior art references individually even though the Examiner relies on the combination of Conte, Hikichi, and Goldberg as teaching or suggesting the disputed features. Final Act. 2-4; Ans. 2-4. In re 3 Appeal 2016-007867 Application 14/161,423 Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012) (citing In re Keller, 642 F.2d 413, 425 (CCPA 1981)) (“The test for obviousness is . . . what the combined teachings of the references would have suggested to those having ordinary skill in the art”). The Examiner found that Conte teaches memory read requests having different priorities being combined into a single data request. Ans. 2 (citing Conte 19, 20). The Examiner also found that Hikichi teaches a pre-fetch request having a lower priority than a read request. Id. (citing Hikichi 1122). The Examiner further found that Goldberg teaches merging/combining data object instances having different priority values, where the merged data object retains a higher priority value associated with one of the data object instances before the merge. Id. at 2—3 (citing Goldberg 134). The Examiner also provided “articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.” See In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006). Appellants present insufficient persuasive argument or objective evidence to rebut the Examiner’s findings. The test for obviousness is not whether the claimed invention is expressly suggested in any one or all of the references, but whether the claimed subject matter would have been obvious to those of ordinary skill in the art in light of the combined teachings of those references. Keller, 642 F.2d at 425. Although Appellants argue that Goldberg’s generic data object instances are “entirely different” than memory read access requests and pre-fetch requests (App. Br. 6), Appellants have not persuasively explained the differences. Appellants also have not persuasively explained why Goldberg’s teaching of values having a high assigned priority overwriting values having a lower priority would not have 4 Appeal 2016-007867 Application 14/161,423 suggested to an artisan of ordinary skill “assigning” a priority to the combined memory access request, as claim 1 requires. For these reasons, we are not persuaded that the Examiner erred in finding that the combination of Conte, Hikichi, and Goldberg teaches or suggests the limitations of claim 1. Accordingly, we sustain the 35 U.S.C. § 103(a) rejection of independent claim 1, as well as the 35 U.S.C. § 103(a) rejection of independent claim 12, which Appellants argue are patentable for similar reasons. App. Br. 7. We also sustain the Examiner’s rejections of dependent claims 2, 4—6, 8—11, 13, 16, and 18—20, for which Appellants make no separate arguments for patentability. Id. See 37 C.F.R. § 41.37(c)(l)(iv) (Arguments not made are waived). DECISION We affirm the decision of the Examiner rejecting claims 1, 2, 4—6, 8-13, 16, and 18-20. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 5 Copy with citationCopy as parenthetical citation