Ex Parte Josef Moeller

Patent Trials and Appeals BoardMay 21, 2013

10349837 - (D) (P.T.A.B. May. 21, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/349,837 01/23/2003 Lothar Benedict Erhard Josef Moeller Moeller 10 (LCNT/124825 a 2321 46363 7590 05/21/2013 WALL & TONG, LLP/ ALCATEL-LUCENT USA INC. 25 James Way Eatontown, NJ 07724 EXAMINER BELLO, AGUSTIN ART UNIT PAPER NUMBER 2637 MAIL DATE DELIVERY MODE 05/21/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte LOTHAR BENEDICT ERHARD JOSEF MOELLER ____________ Appeal 2010-012533 Application 10/349,837 Technology Center 2600 ____________ Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and CARLA M. KRIVAK, Administrative Patent Judges. KRIVAK, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of claims 1-23. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appeal 2010-012533 Application 10/349,837 2 STATEMENT OF THE CASE Appellant’s claimed invention is directed to a method and apparatus for improving jitter tolerance when receiving optical signals in optical transmission systems (Spec. 1:11-13). Independent claim 1, reproduced below, is representative of the subject matter on appeal. 1. A method for improving the jitter tolerance of a receiver in an optical transmission system, comprising: receiving an input optical signal; sampling said input signal at least twice within its bit slot; and determining, using logical OR function circuitry processing a combination of at least two of said samples, a resulting logic state of an output signal associated with said input signal, wherein said output signal exhibits an improved bit error rate (BER). REFERENCE and REJECTION The Examiner rejected claims 1-23 under 35 U.S.C. § 103(a) based upon the teachings of McCormack (U.S. Patent 6,463,109 B1, issued October 8, 2002). ANALYSIS Appellant contends McCormack does not suggest the steps of sampling an input signal at least twice within its bit slot and determining a resulting logic state of an output signal associated with the input signal (App. Br. 13). Rather, Appellant asserts, McCormack discloses a single sample of an input signal is used to determine the logic state of the output signal associated with the input signal (id.). Appellant then contends a delay Appeal 2010-012533 Application 10/349,837 3 is associated with processing data samples from data and monitor channels and thus, McCormack does not suggest using both the data channel sample and the monitor channel sample to determine the output signal associated with the input signal as claimed (App. Br. 14-15). We adopt the Examiner’s findings as our own and provide the following comments. Appellant’s claim includes three steps: 1) receiving; 2) sampling; and 3) determining, and Appellant’s invention is directed to improving jitter tolerance by outputting a signal having an improved bit error rate (BER). The Examiner finds McCormack discloses sampling an input signal at least twice within its bit slot (the data channel samples and compares an output of an optical receiver, forming a data out signal and a monitor channel also samples and compares the output of the optical receiver (Ans. 7-8; McCormack, col. 4, l. 65-col. 5, l. 4)) and determines a logic state of an output signal associated with the input signal (Ans. 3-4). Thus, McCormack discloses sampling the same signal twice within the same bit slot as claimed (Ans. 8). The Examiner then states although McCormack teaches an XOR gate, one of skill in the art would know how to employ OR logic gate circuitry (Ans. 4). We are not persuaded the Examiner’s reading of the claims on the cited combination of references is overly broad, unreasonable, or inconsistent with the Specification. For the above reasons, we are not persuaded of Examiner error. We find the weight of the evidence supports the Examiner’s underlying factual findings and ultimate legal conclusion of obviousness, and therefore sustain the Examiner’s rejection of claim 1, and claims 2-13, depending therefrom and argued together (App. Br. 17). Appeal 2010-012533 Application 10/349,837 4 With respect to claims 14-21, 22, and 23, although Appellant has separate headings for these claims, they recite the same arguments as those set forth above with respect to claim 1 (App. Br. 18-20). Additionally, Appellant asserts these claims are allowable “at least for the same reasons provided herein with respect to claim 1” (id.). Thus, as we have sustained the Examiner’s rejection of claims 1-13, for the above reasons, we also sustain claims 14-23. DECISION The Examiner’s decision rejecting claims 1-23 under 35 U.S.C. § 103 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED pgc