Ex Parte Jackson

Patent Trial and Appeal BoardMar 22, 2018

14798841 (P.T.A.B. Mar. 22, 2018)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/798,841 07/14/2015 Hugh Jackson 075803.000025 2722 125968 7590 03/26/2018 Vorys, Sater, Seymour and Pease LLP (ImgTec) 1909 K St., N.W. Ninth Floor Washington, DC 20006 EXAMINER VICARY, KEITH E ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 03/26/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patlaw @ vorys. com vmdeluc a @ vorys. com rntisdale@vorys.com PTOL-90A (Rev. 04/07) UNITED STATES PATEN AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte HUGH JACKSON Appeal 2017-009667 Application 14/798,8411 Technology Center 2100 Before JOHN A. EVANS, JAMES W. DEJMEK, and JASON M. REPKO, Administrative Patent Judges. EVANS, Administrative Patent Judge. DECISION ON APPEAL Appellant2 seeks our review under 35 U.S.C. § 134(a) from the Examiner’s final rejection of Claims 1—18. App. Br. 1. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE.3 1 The present application is subject of a petition for Participation in the Global/IP5 Patent Prosecution Highway Pilot Program, granted April 7, 2016. 2 Appellant states the real party in interest is Imagination Technologies Limited. App. Br. 2. 3 Rather than reiterate the arguments of the Appellant and the Examiner, we refer to the Appeal Brief (filed February 22, 2017, “App. Br.”), the Reply Appeal 2017-009667 Application 14/798,841 STATEMENT OF THE CASE The claims relate to a processor and method of efficiently running a 32-bit operating system on a 64-bit processor. See Abstract. INVENTION Claims 1,10, and 18 are independent. An understanding of the invention can be derived from a reading of Claim 1, which is reproduced below: 1. A processor arranged to run software and having a first mode of operation in which the processor operates as a single- threaded (nX)-bit processor and a second mode of operation in which the processor operates as an n-threaded X-bit processor, where n and X are positive integers greater than one and nX is n multiplied by X, the processor comprising: one or more configuration registers arranged to store a single configuration parameter, the configuration parameter indicating a width of software visible registers; a fetch stage arranged in the first mode of operation to fetch instructions from a single thread of the software and in the second mode of operation to fetch instructions from each of n threads of the software and to switch between the first and second modes of operation dependent upon a value of the configuration parameter; a register file comprising a plurality of general purpose registers; control logic associated with the register file and arranged, in the second mode of operation, to logically divide Brief (filed July 5, 2017, “Reply Br.”), the Examiner’s Answer (mailed May 4, 2017, “Ans.”), the Final Action (mailed August 3, 2016, “Final Act.”), and the Specification (filed October 3, 2016, “Spec.”) for their respective details. 2 Appeal 2017-009667 Application 14/798,841 the register file into n portions and to control access to the portions, each portion being arranged to store data for one of the n threads of the software and arranged to switch between the first and second modes of operation dependent upon the value of the configuration parameter; and one or more execution units arranged to execute instructions from the single thread in the first mode of operation and to execute instructions from the n threads in the second mode of operation and-to switch between the first and second modes of operation dependent upon the value of the configuration parameter. References and Rejections Chen, et al., Donovan, et al., Hake will, et al., Boggs, et al., Davis, et al., Abernathy, et al., Henmi Hansen, et al., US 2004/0221122 Al Nov. 4, 2004 US 2004/0230972 Al Nov. 18, 2004 US 6,862,563 B1 Mar. 1,2005 US 7,051,329 B1 May 23, 2006 US 2006/0265576 Al Nov. 23, 2006 US 2007/0198814 Al Aug. 23, 2007 US 2007/0266387 Al Nov. 15, 2007 US 2008/0104375 Al May 1, 2008 The claims stand rejected as follows: 1. Claims 1—9 and 18 stand rejected under 35 U.S.C. § 112(a), as failing to comply with the written description requirement. Final Act. 15-19. 2. Claims 1—9 and 18 stand rejected under 35 U.S.C. § 112(b), as indefinite. Final Act. 19—22. 3 Appeal 2017-009667 Application 14/798,841 3. Claims 1, 3—5, 10, 12, and 13 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis and Henmi. Final Act. 23— 31. 4. Claims 2 and 11 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, and Chen. Final Act. 31—34. 5. Claims 6 and 14 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, and Hansen. Final Act. 34—37. 6. Claims 7 and 15 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, and Boggs. Final Act. 37 40. 7. Claims 8 and 16 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, Boggs, and Abernathy. Final Act. 40-42. 8. Claims 9 and 17 stand rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, and Donovan. Final Act. 42-44. 9. Claim 18 stands rejected under 35 U.S.C. § 103 as being unpatentable over Davis, Henmi, and Hakewill. Final Act. 44-48. ANALYSIS We have reviewed the rejections of Claims 1—18 in light of Appellants’ arguments that the Examiner erred. We are persuaded that Appellant identify reversible error. We consider Appellant’s arguments seriatim, as they are presented in the Appeal Brief, pages 6—15. Claims 1-9 and 18: Written Description and Indefiniteness. Claims 1—9 and 18 stand rejected under 35 U.S.C. § 112(a), as failing to comply with the written description requirement and under § 112(b) as indefinite in view of the Examiner’s finding that various elements recited by 4 Appeal 2017-009667 Application 14/798,841 Claims 1, 6, 8, and 18 invoke the “means plus function” claim interpretation rule of 35 U.S.C. § 112(f), where the specification fails to disclose the corresponding structure, material, or acts for the claimed function. See Final Act. 15—22; App. Br. 6. In particular, the Examiner finds the recitations “control logic . . .,” of Claim 1; “arbitration logic . . .,” of Claim 6; “flushing logic . . .,” of Claim 8; and “control logic . . .,” of Claim 18, each invoke 35 U.S.C. § 112(f) but lack sufficient written description to disclose the corresponding function. Final Act. 15-16. In view of the written description finding, Claims 1—9 and 18 further stand rejected under 35 U.S.C. § 112(b), as indefinite. Final Act. 19—22. Appellant contends the Specification provides the structure, required to overcome a written description rejection, at least in Paragraph 56 that discloses, inter alia: a particular reference to “logic” refers to structure that performs a function or functions. An example of logic includes circuitry that is arranged to perform those fimction(s). For example, such circuitry may include transistors and/or other hardware elements available in a manufacturing process. Id. 6. Appellant further contends that it is well-established that the structure required under 35 U.S.C. § 112(f) for a limitation reciting “means for” performing a specific computer-implemented function, may merely be the algorithm needed to transform a general purpose computer or microprocessor disclosed in the specification. App. Br. 7—8 (citing Aristocrat Techs. Australia Pty Ltd. v. Int’l Game Tech., 521 F.3d 1328, 1333 (Fed. Cir. 2008); Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323, 1340 (Fed. Cir. 2008); IVMS Gaming, Inc. v. Inti Game Tech., 184 F.3d 1339, 1349 (Fed. Cir. 1999). Appellant argues that such an algorithm is 5 Appeal 2017-009667 Application 14/798,841 fully disclosed in Fig. 4 in the form of a flow diagram that explains the logical operations of a processor according to the claimed invention. The Examiner finds the algorithm of Figure 4 fails to fully specify each step and specialized function that must be performed. See Ans. 49-51. Appellant replies the omitted steps, such as dividing a register into n portions, are not specialized functions, and would have been recognized as such by a person of ordinary skill in the art. Reply 3. We agree with Appellant. As an example of a specialized function, the Examiner finds that Figure 4 “neither discloses logically dividing the register file into n portions and controlling access to the portions, each portion being arranged to store data for one of the n threads of the software.” Ans. 49. However, the Final Action found this limitation is taught by Davis. Final Act. 24 (citing Davis, 133,11. 1—7). A finding that the limitation is in the prior art is inconsistent with a finding that the limitation must be taught to a person of ordinary skill in the art. Claim 18: Written Description. Claim 18 recites, inter alia, “one or more configuration registers arranged to store a single configuration parameter.” The Examiner finds the Specification discloses “a single configuration bit which indicates whether the operating system is 64-bit or 32-bit,” but the Examiner finds “a configuration register storing a configuration parameter, wherein the configuration parameter is a single bit, is not necessarily the same as a configuration register storing a single configuration parameter.” Final Act. 18—19. We disagree with the Examiner and find the written description 6 Appeal 2017-009667 Application 14/798,841 adequate to apprise a person of ordinary skill in the art of the bounds of the limitation. We find Claims 1—9 and 18 are adequately supported by written description under § 112(a) and are not indefinite under § 112(b). Claims 1-18: Obviousness over Davis and Henmi AND VARIOUSLY IN VIEW OF SECONDARY REFERENCES. Claims 1—18 stand rejected under the basic combination of Davis and Henmi and various subsets of the claims stand further rejected in view of secondary references. See Final Act. 23—48. Appellant argues all claims stand or fall in view of the limitations of Claim 1. App. Br. 10. A configuration parameter indicating a width of software visible registers. Appellant contends the cited art fails to teach either software-visible registers or a configuration parameter indicating a width of a software- visible register. Id. The Examiner finds Davis teaches a first mode of operation, 32 bit, which indicates a 32-bit width of general purpose registers and similarly, Davis teaches a second, 64-bit, mode which teaches a second, 64-bit, width of general purpose registers. Ans. 53. Appellant replies that the cited portions of Davis merely state that a first mode of operation may be a 32-bit mode wherein instructions associated with 32-bit operands are executed and stored in a general purpose register of a first array 103 and that in a second mode of operation, registers 104 in both first array 103 and second array 105 may be employed to store an operand associated with an instruction requiring 64-bit operands. Reply Br. 4—5. Appellant argues the Examiner concedes Davis does not describe any indication of software visible registers, and thus, Davis consequently 7 Appeal 2017-009667 Application 14/798,841 also cannot contain any description of the width of such non-described software visible registers. Id., 5. Appellant contends the cited portions of Henmi disclose a multithread mode register 214a, which is part of a configuration register group 2100 of a thread execution scheduler unit 210 which holds mode information indicating either a single thread mode or a multithread mode. Id. Appellant argues Henmi fails to describe any parameter indicating a width of software visible registers. Id. Appellant further argues because neither reference describes the width of a software- visible register, then consequently, no combination thereof can teach the claimed feature. Id. The Examiner finds Davis teaches a first mode of operation indicates a 32-bit width of general-purpose registers. Final Act. 23—24 (citing Davis 132). Davis discloses: The first mode may be a thirty-two bit mode in which the exemplary processing system 100 receives instructions for execution by a first thread associated with 32-bit operands. Davis 132,11. 3—6 (cited by the Examiner). We fail to find a teaching of the width of a software-readable register. Moreover, Davis also discloses that in: some embodiments, each register 104 of the exemplary processing system 100 is adapted to store thirty two bits of data (although one or more of the registers 104 may store a larger or smaller amount of data). Davis 131,11. 1^4. Davis discloses registers of variable width are accessible by threads operating with 32-bit operands. The Examiner does not rely upon 8 Appeal 2017-009667 Application 14/798,841 Henmi to teach the claimed “parameter indicating a width of software visible registers”: Note that the prior art rejection of claim 1 cited paragraph [0048] of Henmi as disclosing “one or more configuration registers arranged to store a single configuration parameter indicating a mode, such that switching between first and second modes of operation is dependent upon a value of the configuration parameter” - not “the configuration parameter indicating a width of software visible registers.” Ans. 54. The Examiner does not cite the supplemental art for this teaching. See Ans. 52—67. We find no disclosure in the cited art that teaches a “configuration parameter indicating a width of software visible registers,” as recited in independent Claims 1 and 18 and as commensurately recited in independent Claim 10. DECISION The rejection of Claims 1—9 and 18 under 35 U.S.C. § 112(a), as lacking written description is REVERSED. The rejection of Claims 1—9 and 18 under 35 U.S.C. § 112(b), as indefinite is REVERSED. The rejection of Claims 1—18 under 35 U.S.C. § 103 is REVERSED. REVERSED 9