Ex Parte Isaacs et al

Patent Trial and Appeal BoardMar 18, 2013

10356917 (P.T.A.B. Mar. 18, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte DANIEL ISAACS, CURTIS SETTLES, and RAFAEL KEDEM1 ____________________ Appeal 2010-009719 Application 10/356,917 Technology Center 2100 ____________________ Before ERIC B. CHEN, TREVOR M. JEFFERSON, and LARRY J. HUME, Administrative Patent Judges. HUME, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) of the Final rejection of claims 1-19, all pending claims in the application. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 The Real Party in Interest is LSI Logic Corporation. (App. Br. 2.). Appeal 2010-009719 Application 10/356,917 2 STATEMENT OF THE CASE 2 The Invention Appellants’ invention generally relates to the field of integrated circuit design, and particularly to a development methodology for integrated circuits, including application specific integrated circuits, general purpose integrated circuits, and system-on-a-chip (SOC). Spec. p. 1, ¶ [0002]. Exemplary Claims Claim 1 is an exemplary claim representing an aspect of the invention which is reproduced below (emphasis added): 1. A method for designing an integrated circuit and software for implementation by the integrated circuit, comprising: receiving a specification for an integrated circuit design, the integrated circuit design specification including desired integrated circuit functionality; modeling the integrated circuit design specification, wherein modeling includes defining a behavioral model of the integrated circuit design specification which includes the desired integrated circuit, the modeling the integrated circuit design specification further including: providing a preconfigured library supporting drag and drop functionality for adding or deleting functionality into the behavioral model; 2 Our decision refers to Appellants’ Appeal Brief (“App. Br.,” filed Jan. 26, 2010); Examiner’s Answer (“Ans.,” mailed Apr. 8, 2010); Final Office Action (“FOA,” mailed Aug. 10, 2009); and the original Specification (“Spec.,” filed Feb. 3, 2003). Appeal 2010-009719 Application 10/356,917 3 simulating the integrated circuit design specification by utilizing the behavioral model as a virtual platform, wherein the virtual platform allows software to run on the virtual platform and on an integrated circuit having the desired integrated circuit functionality; and validating the software on the integrated circuit for functional correctness and proper orientation of the integrated circuit design prior to first silicon, further including: transferring the simulated integrated circuit design specification to a user on a computer readable medium including a preconfigured virtual model to allow a trial of the integrated circuit design, further including: allowing the user to write software against the preconfigured virtual model via a license provided to enable the customer to author and manipulate the integrated circuit design and create a custom type of module which may incorporate IP specific to the user. Prior Art The Examiner relies upon the following prior art in rejecting the claims on appeal: Rostoker US 5,933,356 Aug. 3, 1999 Bade US 2002/0059054 A1 May 16, 2002 Rejections on Appeal 3 Claims 1-19 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Rostoker and Bade. Ans. 3. 3 We note that the rejection of claims 1, 7, 11, and 16 as being unpatentable over the combination of Rostoker, Hegde, and Bade has been withdrawn by the Examiner. Ans. 2-3. Appeal 2010-009719 Application 10/356,917 4 ISSUE Appellants argue (App. Br. 11-18) that the Examiner’s unpatentability rejection of claim 1 under 35 U.S.C. § 103(a) over the combination of Rostoker and Bade is in error. These contentions present us with the following issue: Did the Examiner err in finding that the combination of Rostoker and Bade teaches or suggests Appellants’ claimed method for designing an integrated circuit and software for implementation by the integrated circuit including, inter alia, the step of “validating the software on the integrated circuit for functional correctness and proper orientation of the integrated circuit design prior to first silicon,” as recited in Claim 1? ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ arguments that the Examiner has erred. We disagree with Appellants’ conclusions with respect to claim 1, and we adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons and rebuttals set forth by the Examiner in the Examiner’s Answer in response to Appellants’ Arguments. However, we highlight and address specific findings and arguments regarding claim 1 for emphasis as follows. We disagree with Appellants’ contention that “[n]owhere in the above recited text is there a disclosure of ‘validating the software on the integrated circuit for functional correctness and proper orientation of the integrated circuit design prior to first silicon,’ as recited in Claim 1.” App. Br. 13 (citing Rostoker at Abstract, col. 8:48-55, and col. 11:64-12:7). Appeal 2010-009719 Application 10/356,917 5 In addition, we note that Appellants’ arguments appear to rely exclusively upon block quotations from the Final Office Action and the cited art, without substantive analysis or explanation of how the claimed invention differs from the cited art, other than reciting portions of the claim limitations and contending that the references do not teach the limitations. App. Br. 11- 16. Such statements are not considered to be arguments. 37 C.F.R. § 41.37(c)(1)(vii) (“A statement which merely points out what a claim recites will not be considered an argument for separate patentability of the claim.”); In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (“[W]e hold that the Board reasonably interpreted Rule 41.37 to require more substantive arguments in an appeal brief than a mere recitation of the claim elements and a naked assertion that the corresponding elements were not found in the prior art.”). Thus, we do not find Appellants’ arguments to be persuasive. We agree with the Examiner’s finding that the combination of Rostoker and Bade teaches or suggests Appellants’ claimed method, including, inter alia, the step of “validating the software on the integrated circuit for functional correctness and proper orientation of the integrated circuit design prior to first silicon,” as recited in claim 1. (Ans. 3-5). In particular, we agree with the Examiner’s response to Appellants’ contentions cited above that: The Examiner respectfully notes that it is the combination of Rostoker and Bade that is relied upon in the rejection, as Rostoker does provide the validation of a software portion of the integrated circuit for functional correctness prior to fabricating the silicon model (see fig.21 (2102-2122), 28, Appeal 2010-009719 Application 10/356,917 6 col.25 line 51-col.26 line 24); as Appellant pointed to Rostoker’s portion not specifically cited by the Examiner, the Examiner further notes that the rejection clearly set forth what is relied upon in the rejection for each limitation. Bade, is used as a secondary reference in the rejection, clearly provides the use of a virtual prototype system used to evaluate and debug the software prior to silicon implementation using a virtual platform (see for example fig. 6, para 91-92, see further para 200,211). Ans. 9. The Examiner’s findings as set forth in the Examiner’s Answer remain unrebutted by Appellants. In addition, we find that the Examiner has provided an extensive mapping of the limitations of claim 1 to the cited art, and has provided a reasoned statement for combining the references in the manner suggested. We agree with the Examiner’s findings of fact and resulting claim construction. Ans. 3-5 and 9-11. Accordingly, Appellants have not provided sufficient evidence or arguments to convince us of any error in the Examiner’s characterization of the cited art and related claim construction. Therefore, we sustain the Examiner’s unpatentability rejection of claim 1. As Appellants have not provided separate arguments with respect to any of claims 2-19, but merely state that these claims stand or fall with independent claim 1 (App. Br. 18), we similarly sustain the Examiner’s rejection of these claims under 35 U.S.C. § 103(a). Appeal 2010-009719 Application 10/356,917 7 CONCLUSIONS The Examiner did not err with respect to the unpatentability rejection of claims 1-19 over the combination of Rostoker and Bade, and the rejection is sustained. DECISION The decision of the Examiner to reject claims 1-19 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011). AFFIRMED msc