Ex Parte Huang et al

Patent Trial and Appeal BoardMar 3, 2017

13460122 (P.T.A.B. Mar. 3, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/460,122 04/30/2012 WEI HUANG AUS920110458US2 9600 75916 7590 IBM AUS IPLAW (GLF) c/o Garg Law Firm, PLLC 4521 Copper Mountain Lane Richardson, TX 75082 EXAMINER DUDEK JR, EDWARD J ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 03/07/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): dpandy a @ garglaw. com uspto@garglaw.com garglaw @gmail.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte WEI HUANG and ANTHONY NELSON HYLICK Appeal 2016-004960 Application 13/460,122 Technology Center 2100 Before JEAN R. HOMERE, JOHN A. EVANS, and DANIEL J. GALLIGAN, Administrative Patent Judges. Per Curiam. DECISION ON APPEAL1 Appellants2 seek our review under 35 U.S.C. § 134(a) of the Examiner’s final rejection of claims 1—10. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 Our Decision refers to Appellants’ Appeal Brief filed October 13, 2015 (“App. Br.”); Appellant’s Reply Brief filed April 4, 2016 (“Reply Br.”); and the Examiner’s Answer mailed February 25, 2016 (“Ans.”). 2 Appellants identify International Business Machines Corporation as the real party in interest. App. Br. 2. Appeal 2016-004960 Application 13/460,122 STATEMENT OF THE CASE Claims on Appeal Claim 1, which is the sole independent claim, is reproduced below: 1. A method for managing a lifespan of a memory device, the method comprising: setting, using a processor, at an application executing in a data processing system, a throttling rate to a first value for processing memory write operations in the memory device, a useful lifespan of the memory device corresponding to a pre-determined number of memory write operations performed in the memory device, the setting using a health data of the memory device for determining the first value; determining whether the health data of the memory device indicates a wear on a cell due to cell to cell variation in the memory device from a first memory write operation of only a specific data pattern in another cell in a neighborhood of the cell; determining whether a second memory write operation can be performed on the memory device within the first value of the throttling rate, the first value of the throttling rate allowing a first number of memory write operations using the memory device per time period; and performing, responsive to the determining that the second memory write operation cannot be performed on the memory device within the first value of the throttling rate, the second memory write operation using a secondary storage device. References Danilak Sharon et al. Maheshwari et al. Rub et al. US 2008/0126891 Al US 2010/0195384 Al US 2012/0017034 Al US 2013/0007343 Al May 29, 2008 Aug. 5, 2010 Jan. 19,2012 Jan. 3, 2013 2 Appeal 2016-004960 Application 13/460,122 Examiner’s Rejections Claims 1—10 stand provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11—17 and 21—23 of copending Application No. 13/308,773. Ans. 2—11. Claims 1—4 and 7—10 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Maheshwari, Danilak, and Sharon. Ans. 11—16. Claims 5 and 6 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Maheshwari, Danilak, Sharon, and Rub. Ans. 16—19. ANALYSIS Double Patenting Rejection The provisional rejection of claims 1—10 on the ground of nonstatutory obviousness-type double patenting is moot because Application No. 13/308,773 is abandoned (Notice of Abandonment mailed Jan. 25, 2016). Therefore, Appellants’ appeal of the Examiner’s provisional rejection of claims 1—10 on the ground of nonstatutory obviousness-type double patenting is dismissed. Independent Claim 1 Appellants argue Sharon does not teach “a first memory write operation of only a specific data pattern in another cell in a neighborhood of the cell,” as recited in claim 1. App. Br. 9-15; Reply Br. 2-4. In particular, Appellants contend Sharon teaches reading information from one or more cells and comparing the read information to a predetermined pattern. App. Br. 12 (citing Sharon || 28—33). Appellants additionally argue Sharon does not teach that, if the read information matches the predetermined pattern, the 3 Appeal 2016-004960 Application 13/460,122 matched information is a result of an overt write operation to the one or more cells. App. Br. 12 (citing Sharon || 28—33). We are not persuaded. The Examiner finds Sharon teaches specific data patterns written to a cell as a result of write operations. Ans. 20 (citing Sharon || 3, 16). Sharon states that “values of the neighboring memory cells may be compared to one or more patterns that are correlated with the particular memory cell being prone to a disturb error that may be caused by a read operation or a write operation to one or more of the neighboring cells.” Sharon 13 (emphasis added). Claim 1 recites “a first memory write operation of only a specific data pattern.” The claim does not define what that pattern must be, nor does the claim require that the pattern be written multiple times. A write operation writes a “specific data pattern,” even if only once. Therefore, the “write operation” in Sharon teaches “a first memory write operation of only a specific data pattern,” and it teaches that a write operation causes the disturb error. See Sharon 13. Appellants further assert that Sharon teaches patterns that are written accidentally and that “[a]n accidental writing of a specific pattern falls outside the reasonable scope of a ‘write operation of only a specific data pattern in another cell in a neighborhood of the cell.’” Reply Br. 2 (emphasis omitted). We disagree. As explained above, claim 1 recites “a first memory write operation of only a specific data pattern.” Even assuming Appellants’ characterization of Sharon as only teaching accidental writing, an accidental write operation is still a write operation. The claims as presented on appeal do not exclude an “accidental” write operation, nor do they define what data must be within the recited “data pattern.” 4 Appeal 2016-004960 Application 13/460,122 We agree with the Examiner that Sharon teaches “a first memory write operation of only a specific data pattern in another cell in a neighborhood of the cell,” and we are not persuaded of error in the Examiner’s conclusion that the subject matter of independent claim 1 would have been obvious based on the combination of Maheshwari, Danilak, and Sharon. As such, we sustain the rejection of independent claim 1 under 35 U.S.C. § 103(a). Remaining Claims Appellants do not present additional persuasive arguments regarding claims 2—10, which depend from claim 1 (App. Br. 15—16; Reply Br. 4), and, therefore, we sustain the rejections of these claims. DECISION We affirm the Examiner’s rejection of claims 1—10 under 35 U.S.C. § 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). Because we have affirmed at least one ground of rejection with respect to each claim on appeal, the Examiner’s decision is affirmed. See 37 C.F.R. §41.50(a)(1). AFFIRMED 5