Ex Parte Hsu

Patent Trial and Appeal Board

Mar 7, 2016

13437397 (P.T.A.B. Mar. 7, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/437,397 04/02/2012 R-Ming Hsu
23524 7590 03/09/2016
FOLEY & LARDNER LLP
3000 K STREET N.W.
SUITE 600
WASHINGTON, DC 20007-5109
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
088245-9805 1004
EXAMINER
GOOD JOHNSON, MOTILEWA
ART UNIT PAPER NUMBER
2616
NOTIFICATION DATE DELIVERY MODE
03/09/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipdocketing@foley.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte R-MING HSU
Appeal2014-003592
Application 13/437,397
Technology Center 2600
Before KRISTEN L. DROESCH, JOHNNY A. KUMAR, and
LINZY T. McCARTNEY, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the rejection of
claims 1-13. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
Appeal2014-003592
Application 13/437 ,397
Claim 1 is illustrative:
Exemplary Claim
1. A system comprising:
an instruction scheduler configured to scan first and
second instructions, wherein the first and second instructions
are operable to output data to different components in a register;
a rule checker configured to determine if the scanned first
and second instructions are data independent;
an instruction combiner configured, in response to a
determination that the scanned first and second instructions are
data independent, to form a combination of the scanned first
and second instructions; and
a processing unit comprising a single decoder, the
processing unit operable to receive the combination, decode the
combination using the single decoder, and execute the
combination.
The Examiner's Rejection
Claims 1-13 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Chang (U.S. Patent 6,301,651 Bl (Oct. 9, 2001)), in view
of Hinton (U.S. Statutory Invention Registration H1291 (Feb. 1, 1994)).
Ans. 3---6; Final Act. 2-5.
ANALYSIS
Rejection of Claim 1 under§ 103
We have considered all of Appellant's arguments and any evidence
presented. We disagree with Appellant's arguments, and we adopt as our
own: ( 1) the findings and reasons set forth by the Examiner in the action
from which this appeal is taken, and (2) the reasons and rebuttals set forth in
the Answer in response to Appellant's arguments. Ans. 7-10. However, we
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Application 13/437 ,397
highlight and address specific findings and arguments for emphasis in our
analysis below.
The Examiner equates the claimed "a register" (Ans. 9; Final Act. 5-
6) to a "global register, local register, or scratch registers" of Hinton, which
in tum may consist of multiple constituent register devices (16 global
registers, 16 local registers, and 4 scratch registers). See Ans. 8; Hinton
column 12, lines 56-68. We agree with the Examiner.
As to Appellant's contention that "[s]imultaneous execution of a read
operation and a write access operation is not the same as 'first and second
instructions' that 'are operable to output data to different components in a
register"' (App. Br. 11-13; Reply Br. 7-8), we agree with the Examiner's
findings that the combination of Chang and Hinton teaches multiple
instructions (Ans. 9). In particular, the Examiner relies upon the citations of
Hinton, at column 7, lines 46-50, and column 13, lines 8-15, which disclose
a memory operation and a logic operation.
The Examiner also finds Chang teaches folding instructions outputted
to a buffer. (Ans. 7-9 (no fold, 2-4 fold)). We agree with the Examiner that
Hinton discloses multiple instructions that could be executed in parallel or
overlapped executions (Ans. 9) and outputting of instructions to different
portions of the register via registry file parallelism (Ans. 8).
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Application 13/437 ,397
We are therefore unpersuaded by Appellant's arguments because the
Examiner found that the combination of prior art taught the claimed
invention (Final Act. 2-3). 1' 2
With regards to Appellant's contentions with respect to on-chip
caching, and overwriting the full contents of the registers being different
than writing to different components of the same register (App Br. 13-14;
Reply Br. 8), we disagree because we find that overwriting the full contents
of a particular register would change the respective components of that
register. See Ans. 8. We also agree with the Examiner that Hinton teaches
writing to different contents of a respective register file (Ans. 10; Hinton
column 13, lines 11-20).
With regards to Appellant's contentions that multiple operations that
are executed in parallel are unrelated operations and are not the same as the
claimed "first and second instructions" (Reply Br. 8-9), we are unpersuaded
because the Examiner relied on Hinton's teachings of one logic operation,
and one memory operation to be performed on every clock cycle to teach the
claimed "first and second instructions." Even if "unrelated" parallel
operations were to be construed as the "first and second instructions" they
would meet the claim limitations because at least two instructions are
executed on a single clock cycle and both instructions are output to the
register file (Hinton column 13, lines 1-20).
1 One cannot show nonobviousness by attacking references individually
when the rejection is based on a combination of references. In re Keller,
642 F.2d 413, 425 (CCPA 1981).
2 Each reference cited by the Examiner must be read, not in isolation, but
for what it fairly teaches in combination with the prior art as a whole. See In
re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
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Application 13/437 ,397
With respect to Appellant's contentions that the Examiner's
discussion of Hinton (Ans. 10; Hinton column 13, lines 40-45) does not
teach outputting to different components of a register, because g4 and g5 are
different registers (Reply Br. 9--10), we disagree because the Examiner relies
upon Hinton's teachings of outputting data to one of a global register, local
register or cache register which are made up of multiple constituent
registers, and such a reading does allow for changing the contents of
multiple register components within that register. (Ans. 8)
Regarding the remaining claims rejected under§ 103, Appellant urges
these claims are patentable by virtue of their respective dependencies from
independent claims 1, 10, and 11. App. Br. 15-16. However, we find no
deficiencies regarding rejection of independent claims 1, 10, and 11, for the
reasons discussed above. Therefore, we sustain the Examiner's rejections of
the remaining claims on appeal for the same reasons discussed above
regarding claims 1, 10, and 11.
DECISION
We affirm the Examiner's rejection of claims 1-13 under 35 U.S.C.
§ 103.
No time for taking any action connected with this appeal may be
extended under 37 C.F.R. § 1.136(a)(l). See 37 C.F.R. § 41.50(±).
AFFIRMED
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