Ex Parte Hsieh et al

Patent Trial and Appeal BoardSep 23, 2014

12831255 (P.T.A.B. Sep. 23, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte HONG-YEAN HSIEH and CHAO-CHENG LEE Appeal 2012-012102 Application 12/831,255 Technology Center 2800 ____________ Before PETER F. KRATZ, MICHAEL P. COLAIANNI, and N. WHITNEY WILSON, Administrative Patent Judges. WILSON, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellants1 appeal under 35 U.S.C. § 134(a) from the decision of the Primary Examiner finally rejecting claims 1–5, and 7–12. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). We reverse. 1 The Real Party-In-Interest is Realtek Semiconductor Corporation (Appeal Br. 2). Appeal 2012-012102 Application 12/831,255 2 CLAIMED SUBJECT MATTER Appellants’ invention is directed to an apparatus for generating an output clock and a method for generating an output clock of a digitally controlled oscillator. Independent claims 1 and 9 are representative of the claims on appeal, and are reproduced below from the Claims Appendix to the Brief (key claim elements in italics): 1. An apparatus for generating an output clock, comprising: a control logic circuit to receive the output clock, a fractional input, and an integer input, the control logic circuit comprising: a fractional waveform generator to generate a fractional control signal according to the output clock and the fractional input; and a controller to generate a plurality of control signals transmitted through word lines and bit lines to a dual bank of tuning cells according to the output clock and the integer input; a LC-tank comprising: an inductance with an inductance value and a capacitor with a first capacitance value; an integer tuning circuit comprising the dual bank of tuning cells, the dual bank is divided into a high bank and a low bank, the high bank and the low bank receiving the plurality of control signals from different word and bit lines to generate a second capacitance value collectively; and a fractional tuning circuit to receive the fractional control signal to generate a third capacitance value. Appeal 2012-012102 Application 12/831,255 3 9. A method for generating an output clock of a digitally controlled oscillator, comprising: receiving the output clock, a fractional input, and an integer input; generating a fractional control signal according to the output clock and the fractional input; generating a plurality of control signals according to the output clock and the integer input; providing a LC-tank which comprises a connection of an inductance with an inductance value and a capacitor with a first capacitance value; providing a second capacitance value according to the plurality of control signals transmitted through different word lines and different bit lines to a high bank and a low bank, the high bank and the low bank determining the second capacitance value collectively; providing a third capacitance value according to the fractional control signal; and outputting the output clock, wherein the oscillating frequency of the output clock corresponds to the inductance value, the first capacitance value, the second capacitance value, and the third capacitance value. DISCUSSION Claims 1–5 and 7–12 stand rejected under 35 U.S.C. § 102(e) as anticipated by Staszewski.2 The Examiner has withdrawn the obviousness rejection over Staszewski (Ans. 3). 2 Staszewski et al., U.S. Patent No. 8,000,428 B2, issued August 16, 2011. Appeal 2012-012102 Application 12/831,255 4 “A prior art reference anticipates a patent claim under 35 U.S.C. § 102(b) if it discloses every claim limitation.” In re Montgomery, 677 F.3d 1375, 1379 (Fed. Cir. 2012) (citing Verizon Servs. Corp. v. Cox Fibernet Va., Inc., 602 F.3d 1325, 1336–37 (Fed. Cir. 2010)). Appellants argue that Staszewski does not disclose a “dual bank” of tuning cells (see, Appeal Br. 9, 17; Reply Br. 2–5).3 The Examiner finds that the “dual bank” limitation in Staszewski’s apparatus in met by the 64-bit integer tuning bank shown in FIG. 17 (Ans. 4). The Examiner finds that the lowest 32 capacitors (those capacitors receiving bits 1-32) may be considered the low bank and the highest 32 capacitors (those receiving bits 33-64) may be considered the high bank (Ans. 7). In response, Appellants argue that the term “bank of tuning cells” as used in the claim means “a group of like-configured or connected capacitors (e.g., a plurality of capacitors connected in parallel),” and that the 64-bit integer tuning bank of Staszewski (which includes 64 parallel-connected capacitors) should be considered to be a single bank (Reply Br. 5).4 Appellants argue that their proposed construction of “bank of tuning cells” is supported both by the Specification5 and a technical definition of “capacitor bank.”6 3 Appellants argue that Staszewski does not disclose a number of additional limitations. We do not address these arguments. 4 The Examiner and Appellants appear to agree that a “bank of tuning cells” has the same meaning as “bank of capacitors” (Ans. 6–7, Appeal Br. 9, Reply Br. 2). 5 As represented by FIG. 4 and the related description (Reply Br. 2–4, citing FIG. 4 and Spec. ¶¶ 41–43). Appeal 2012-012102 Application 12/831,255 5 We find Appellants’ arguments persuasive. The Examiner’s construction of the claims, which would permit a requirement of two banks of tuning cells to be met by a single grouping of capacitors, is not supported by the plain meaning of “dual,” the Specification, or an outside definition of the term “capacitor bank.” Therefore, we agree with Appellants that Staszewski does not disclose the dual bank of tuning cells recited in claim 1 or the “high bank” and “low bank” recited in both claims 1 and 9. Accordingly, we reverse the anticipation rejection over Staszewski. CONCLUSION We REVERSE the rejection of claims 1–5 and 7–12 under 35 U.S.C. § 102(e) as anticipated by Staszewski. REVERSED cdc 6 “A capacitor bank is a grouping of several identical capacitors interconnected in parallel or in series with one another” (Reply Br. 4–5, citing http://www.wisegeek.org/what-is-a-capacitor-bank.htm).