Ex Parte Hatade

Patent Trial and Appeal Board

Jan 10, 2017

13789012 (P.T.A.B. Jan. 10, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/789,012 03/07/2013 Kazunari HATADE 412363US20DIV 2525
22850 7590 01/12/2017
OBLON, MCCLELLAND, MAIER & NEUSTADT, L.L.P.
1940 DUKE STREET
ALEXANDRIA, VA 22314
EXAMINER
WRIGHT, TUCKER J
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
01/12/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patentdocket @ oblon. com
oblonpat @ oblon. com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KAZUNARI HATADE1
Appeal 2015-007052
Application 13/789,012
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CHRISTOPHER C. KENNEDY,
and JENNIFER R. GUPTA, Administrative Patent Judges.
KENNEDY, Administrative Patent Judge.
DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject claims 1 and 8. We have jurisdiction under 35 U.S.C.
§ 6(b).
We AFFIRM-IN-PART.
BACKGROUND
The subject matter on appeal relates to a high-voltage semiconductor
device. E.g., Spec. 1:15—16; Claim 1. Claim 1 is reproduced below from
page 13 (Claims Appendix) of the Appeal Brief:
1 According to the Appellant, the real party in interest is Mitsubishi Electric
Corporation. Br. 1.
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1. A horizontal semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a semiconductor region of a second conductivity type having a
same doping concentration at least in a portion thereof extending
from an upper surface of the semiconductor region in contact
with an oxide film to a bottom surface of the semiconductor
region formed on and in contact with said semiconductor
substrate;
a collector layer of the first conductivity type formed within a
central portion of said semiconductor region and in contact with
a collector electrode;
a base layer of the first conductivity type formed within a
peripheral portion of said semiconductor region such that said
base layer is separated from and surrounds said collector layer;
and
a first emitter layer of the second conductivity type formed in
said base layer, wherein movement of carriers between said first
emitter layer and said collector layer is controlled in a channel
region formed in said base layer, and wherein
a region of the first conductivity type is disposed in said
semiconductor region to contact with the bottom surface of said
base layer.
REJECTIONS ON APPEAL2
1. Claim 1 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Adler et al. (US 4,963,951, issued Oct. 16, 1990) in view of Suzuki et
al. (US 2002/0125542 Al, published Sept. 12, 2002) and Endo et al. (US
5,869,850, issued Feb. 9, 1999).
2. Claim 8 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Adler in view of Nakagawa et al. (US 6,064,086, issued May 16, 2000)
2 In an Advisory Action dated November 19, 2014, the Examiner withdrew a
rejection of claim 8 under 35 U.S.C. § 112,11.
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ANALYSIS
Rejection 1
After review of the cited evidence in the appeal record and the
opposing positions of the Appellant and the Examiner, we determine that the
Appellant has not identified reversible error in the Examiner’s rejection.
Accordingly, we affirm the rejection for reasons set forth below, in the Final
Action, in the Advisory Action, and in the Examiner’s Answer. See
generally Final Act. 4—6, 9; Advisory Act. 2; Ans. 2—8.
The Examiner finds, inter alia, that Adler teaches a horizontal
semiconductor device comprising “a collector layer of the first conductivity
type” that is “in contact with a collector electrode,” as recited by claim 1.
Final Act. 4. The Examiner principally relies on Figure 1 of Adler,
reproduced below:
Figure 1 of Adler depicts “a cross-sectional illustration of a conventional
insulated gate transistor.” Adler at 4:36—37. More specifically, it depicts
layer 18, which, as shown, is a layer of the first conductivity type (p-type)
formed within semiconductor region 14 and in contact with electrode 20.
See id. at 5:56—6:45. The Examiner determines that Adler’s layer 18
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corresponds to the claimed “collector layer of the first conductivity type.”
Final Act. 4.
In the Appeal Brief, the Appellant argues that Adler’s p-type layer 18
is disclosed as an “anode layer” and therefore is not a “collector layer” as
required by claim 1. Br. 5—6 (emphasis in original). The Appellant further
argues that, as demonstrated by Figure 2 of Adler, layer 18 “is actually
effectively functioning as two transistor emitters, not as a collector.” Id.
at 6.
In the Answer, the Examiner compares the structure of Adler Figure 1
with the structure of the Appellant’s Figure 2 and determines that “Adler’s
layer 18 is structurally indistinguishable from the claimed collector layer,
despite being called an anode layer.” Ans. 2—3. The Examiner
acknowledges Figure 2 of Adler but finds the Appellant’s arguments
concerning that figure unpersuasive because:
The circuit shown in FIG. 2 is merely an example of one biasing
arrangement applied to the device of FIG. 1 and would look
different if a different biasing arrangement were used. The
device shown in FIG. 1 of Adler is capable of operating using
different biasing and as such is capable of operating in the same
manner as the claimed device since it has all of the claimed
elements arranged in the claimed and disclosed . . . relative
locations.
Ans. 3.
Essentially for reasons set forth by the Examiner, see Ans. 2—7, we are
not persuaded by the Appellant’s argument. The Examiner recognizes that
Adler does not ipsis verbis describe layer 18 as a collector layer. Id. The
Examiner recognizes that Figure 2 of Adler demonstrates a biasing
arrangement in which layer 18 of Adler functions as an emitter rather than a
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collector. Id. The Examiner, however, finds that Adler’s structure is in
relevant part indistinguishable from the claimed structure, and that a person
of ordinary skill in the art would have known that applying a different
biasing arrangement to Adler’s structure would result in Adler’s structure
functioning in the same manner recited by the Appellant in claim 1. Id. The
Appellant does not file a Reply Brief to contest the Examiner’s findings on
those points. On this record, we have no persuasive basis to reject those
findings.
Although we agree with the Appellant that the prior art must be
considered as a whole, we disagree with the Appellant’s assertion that the
Examiner’s rationale “ignore[s]” Figure 2 of Adler. See, e.g., Br. 7. As
explained above, the Examiner explicitly considers Figure 2 and finds that
the Appellant’s arguments concerning that figure do not persuasively
account for the fact that a person of ordinary skill in the art would have
understood that different biasing arrangements could be applied to the
structure of Figure 1. See, e.g., Ans. 5.
For reasons explained by the Examiner, see Ans. 2—7, we likewise are
unpersuaded by the Appellant’s arguments that the device of Adler’s
Figure 1 “can only perform as intended when it is connected as suggested by
the language used to describe the device connection terminals in both Fig. 1
and Fig. 2,” and that use of a different biasing arrangement would render the
structure of Adler Figure 1 unsuitable to perform as intended or otherwise
impermissibly change the principle of operation of Adler’s structure, see
Br. 8. The Appellant provides no persuasive evidence in support of those
contentions. See In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974)
(“Attorney’s argument in a brief cannot take the place of evidence.”). As the
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Examiner explains, a person of ordinary skill would have understood that
different biasing arrangements could be used with the structure of Adler
Figure 1. See Ans. 2—7. Moreover, the Examiner finds that Figure 1 of
Adler actually shows N+ layer 30 as the emitter because electrode 32 is
described as the source of electron current. Ans. 4; Adler at 6:11—23; see
also Advisory Act. | 6. The Examiner finds that a person of ordinary skill
would have understood that the only other terminal available—electrode 20
in connection with p-type layer 18, see Adler Fig. 2—must be the collector.
Ans. 4. Those findings, which the Appellant does not persuasively address,
support the Examiner’s determination that different biasing arrangements
could be used in connection with the structure of Adler Fig. 1 to result in a
structure in which layer 18 of Adler is a collector layer.
On this record, we are not persuaded that Adler does not teach,
suggest, or otherwise render obvious a structure having the collector layer
required by claim 1,3
Claim 1 also recites that “a region of the first conductivity type is
disposed in said semiconductor region to contact with the bottom surface of
said base layer.” The Examiner finds that Suzuki “discloses a similar device
having a p-type region (114) disposed in said semiconductor region to
contact with the bottom surface of said base layer.” Final Act. 5. The
3 Additionally, we note that the Appellant’s Figure 50, which is designated
as prior art, also discloses a similar IGBT device that possesses the claimed
collector layer. See Spec. 1:23—25 & Fig. 50. In the event of further
prosecution of the application involved in this appeal, we encourage the
Examiner to consider whether claim 1 would have been obvious over the
admitted prior art (e.g., Spec. 1:19—2:24 & Figs. 49, 50) in view of Suzuki
and Endo. See 37 C.F.R. § 41.50(b) (issuance of a new ground of rejection
is at the discretion of the Board).
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Examiner finds that it would have been obvious “to form a region of the first
conductivity type in said semiconductor region to contact with the bottom
surface of said base layer” in Adler “[t]o improve a capability or
ruggedness” of the semiconductor device, as taught by Suzuki. Id.
In opposition to the Examiner’s reasoning, the Appellant first
identifies certain differences between Suzuki and Adler and argues that “[t]o
whatever extent that adding layer 114 as in Fig. 2 of Suzuki can be said to
improve latch up ruggedness as to the collector region of Fig. 1 of Suzuki,
this is not seen to be an automatic benefit as to the different cathode region
of Fig. 1 of Adler.” Br. 9. That argument is not persuasive. “Obviousness
does not require absolute predictability of success. ... all that is required is a
reasonable expectation of success.” In re O'Farrell, 853 F.2d 894, 903—04
(Fed. Cir. 1988). As the Examiner explains, the relevant structures of
Suzuki and Adler appear to be the same, or at least very similar. Ans. 8;
compare Suzuki Fig. 2 with Adler Fig. 1. Both Suzuki and Adler describe
IGBT (insulated gate bipolar transistor) devices. Even assuming the
Appellant’s identification of differences to be correct, the Appellant fails to
explain why those differences would have discouraged a person of ordinary
skill in the art from combining Suzuki and Adler as proposed by the
Examiner, given Suzuki’s express teaching that the modification improves
ruggedness in a similar device. See Suzuki 113.
The Appellant also argues that “Suzuki teaches away from actually
using layer 114 in paragraph [0014] due to undesirable current-voltage
characteristic effects.” Br. 9. That argument is not persuasive for reasons
that the Examiner explains. See Ans. 8. Suzuki 114 describes a certain
scenario in which undesirable current-voltage characteristic effects may be
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observed, see 114 (“if the p-type diffusion layer 114 diffuses to a
prospective channel region below the gate electrode . . . .”), but it does not
suggest that those effects are always observed. As the Examiner explains,
Suzuki simply “highlights design/manufacturing considerations when
implementing layer 114.” Ans. 8; cf. Winner Int 7 Royalty Corp. v. Wang,
202 F.3d 1340, 1349 n.8 (Fed. Cir. 2000) (“The fact that the motivating
benefit comes at the expense of another benefit. . . should not nullity its use
as a basis to modify the disclosure of one reference with the teachings of
another. Instead, the benefits, both lost and gained, should be weighed
against one another.”). On this record, we are not persuaded that Suzuki
teaches away from the combination proposed by the Examiner. See In re
Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004) (for a reference to teach away,
it must “criticize, discredit, or otherwise discourage” the claimed solution).
We have carefully considered the Appellant’s arguments, but we are
not persuaded of reversible error in the Examiner’s rejection of claim 1.
Rejection 2
Claim 8 stands rejected under 35 U.S.C. § 103(a) as unpatentable over
Adler in view of Nakagawa. Claim 8 is reproduced below from pages 13—14
(Claims Appendix) of the Appeal Brief (last paragraph break and indentation
added):
8. A horizontal semiconductor device having multiple unit
semiconductor elements, each of said unit semiconductor
elements formed as an IGBT, comprising:
a semiconductor substrate of a first conductivity type;
a semiconductor region of a second conductivity type having a
same doping concentration at least in a portion thereof extending
from an upper surface of the semiconductor region in contact
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with an oxide film to a bottom surface of the semiconductor
region formed on and in contact with said semiconductor
substrate;
a collector layer of the first conductivity type formed within said
semiconductor region;
a base layer of the first conductivity type formed within said
semiconductor region such that said base layer is off said
collector layer; and
a first emitter layer of the second conductivity type formed in
said base layer,
wherein the semiconductor elements are positioned so that
each first emitter layer of each corresponding semiconductor
element is adjacent to the first emitter layer of each adjacent
semiconductor element with no dielectric layer being between
adjacent first emitter layers and movement of carriers between
each said first emitter layer and each collector layer of a
corresponding semiconductor element is controlled in a
channel region formed in said base layer of each
corresponding semiconductor element.
The Examiner relies on Figure 1 of Adler as discussed above, but
finds, inter alia, that Adler does not disclose a semiconductor comprising
multiple unit semiconductor elements in which “the semiconductor elements
are positioned so that each first emitter layer of each corresponding
semiconductor element is adjacent to the first emitter layer of each adjacent
semiconductor element with no dielectric layer being between adjacent first
emitter layers” as recited by claim 8. Final Act. 7. The Examiner finds,
however, that Nakagawa discloses similar IGBT devices comprising
multiple unit semiconductor elements “wherein the semiconductor elements
are positioned so that each first emitter layer (37) of each corresponding
semiconductor element is adjacent to the first emitter layer of each adjacent
semiconductor element with no dielectric layer being between adjacent first
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emitter layers.” Id. at 8 (citing Nakagawa Figs. 26 and 27, col. 1:50—55, col.
17:59-60). The Examiner finds that “Nakagawa discloses that such an
arrangement of IGBT devices can handle large current density and has a
decreased ON resistance.” Ans. 8. The Examiner concludes that “it would
have been obvious ... to form a plurality of individual IGBT devices
(semiconductor elements) disclosed by Adler and arrange them as disclosed
by Nakagawa” “[t]o handle large current density and decrease ON
resistance.” Id.
The Appellant argues that Figures 26 and 27 of Nakagawa depict a
dielectric oxide layer between the adjacent semiconductor units DU21 and
DU22, and that Nakagawa therefore does not meet the requirement of
claim 8 of “no dielectric layer being between adjacent first emitter layers.”
Br. 10-11.
We agree with the Appellant. With reference to Figure 27 of
Nakagawa, the Examiner apparently interprets the word “between” as
contemplating only a horizontally planar relationship among adjacent
emitter layers. See Ans. 10 (“Gate oxide layer 61 is formed above the plane
connecting the adjacent emitter layers and as such is not between them.”).
However, we must interpret “between” according to its broadest reasonable
interpretation consistent with the Specification. See, e.g., In re Bigio, 381
F.3d 1320, 1324 (Fed. Cir. 2004). The Specification appears to use the word
“between” to refer to elements that are positioned horizontally between two
other elements even if the elements are vertically above or below each other.
For example, with reference to Figure 2, the Specification describes field
oxide film 8 as being “located between n-type buffer layer 3 and the p-type
base layer 5” (emphasis added), notwithstanding the fact that layer 8 is
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described as being formed “on the surface” of layer 2, while layers 3 and 5
are described as being formed “in” layer 2. See Spec. 9:6—19. Using the
Examiner’s analysis, see Ans. 9, it appears that a straight horizontal line
could be drawn between layers 3 and 5, and that layer 8 is vertically above
layers 3 and 5, see Spec. Fig. 2. The Specification nevertheless describes
layer 8 as being located “between” layers 3 and 5.
Given that usage of the word “between” in the Specification, and the
fact that we must interpret the word “between” according to its broadest
reasonable interpretation consistent with the Specification, we agree with the
Appellant that layer 61 of Nakagawa Figure 27 appears “between” adjacent
emitter layers 37. Additionally, we note that if layer 61 were depicted in a
top-down perspective (see, e.g., Fig. 26), rather than only a cross-sectional
perspective (see, e.g., Fig. 27), it would appear to be “between” adjacent
layers 37. Thus, at least to some extent, whether a given layer is “between”
two other layers depends on the perspective used, and the Specification is
consistent with considering a top-down perspective. See, e.g., Spec. 9:6—19,
Figs. 1 & 2.
The Examiner argues that the Examiner’s interpretation of “between”
is consistent with the Appellant’s argument “that Fig. 1 shows a top view
that clearly illustrates that there is no dielectric layer between adjacent first
emitter layers.” Ans. 10 (describing an argument made by the Appellant in
an office action response dated November 11, 2014). However, it is unclear
how the Appellant’s argument concerning Figure 1 supports the Examiner’s
interpretation of the term “between,” particularly in light of the way that
term is used by the Appellant in the Specification. In combination, the
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Appellant’s Figures 1 and 2 support the Appellant’s position that no
dielectric layer exists between adjacent n-type emitter layers 6.
On the record before us, it appears that the spatial relationship of
Nakagawa’s layers 61 and 37 is similar to or the same as the spatial
relationship between Figure 2’s elements 3,5, and 8, with layer 8 being
described as being located “between” layers 3 and 5. A preponderance of
the evidence does not support the Examiner’s determination that
Nakagawa’s layer 61 is not “between” adjacent emitter layers 37 as the
Appellant has used the word “between” in the Specification. See Nakagawa
Fig. 27. Accordingly, we cannot sustain the Examiner’s stated rejection of
claim 8.4
CONCLUSION
We AFFIRM the Examiner’s rejection of claim 1.
We REVERSE the Examiner’s rejection of claim 8.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED-IN-PART
4 In the event of further prosecution of the application involved in this
appeal, we encourage the Examiner to consider whether side-by-side
arrangement of two IGBTs depicted in Figures 49 and 50 of the
Specification, and designated as a prior art, would satisfy the limitations of
claim 8 (see, e.g., Spec. 1:19—2:24 & Figs. 49, 50 (admitted prior art);
compare Spec. Figs. 1 & 2 with Figs. 49 & 50; see also Nakagawa at 17:29-
35 & Fig. 26 (disclosing IGBT having multiple unit semiconductor elements
arranged side-by-side)).
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