Ex Parte Guillemin et al

Patent Trial and Appeal Board

Oct 17, 2017

13543673 (P.T.A.B. Oct. 17, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/543,673 07/06/2012 Pierre Guillemin 852663.599 1096
38106 7590 10/19/2017
Need TP T aw Orniin T T P/NT fFP ORTOTNATTNOT
EXAMINER
701 FIFTH AVENUE, SUITE 5400
SEATTLE, WA 98104-7092
MEHTA, JYOTI
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
10/19/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Patentlnfo @ SeedIP. com
US PTOe Action @ S eedIP .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PIERRE GUILLEMIN and WILLIAM ORLANDO
Appeal 2016-008544
Application 13/543,673
Technology Center 2100
Before CARL W. WHITEHEAD JR., KEVIN C. TROCK, and
AMBER L. HAGY, Administrative Patent Judges.
HAGY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants1 appeal under 35 U.S.C. § 134(a) from the Examiner’
Final Rejection of claims 1—20. We have jurisdiction over these claims
under 35 U.S.C. § 6(b).
We affirm.
1 Appellants identify the real party in interest as STMicroelectronics
(Rousset) SAS. (App. Br. 2.)
Appeal 2016-008544
Application 13/543,673
STATEMENT OF THE CASE
Introduction
According to Appellants, their invention “relates to the protection of a
microprocessor against stack overflow.” (Spec. 12.)
Exemplary Claim
Claims 1, 12, and 17 are independent. Claim 1, reproduced below, is
exemplary of the claimed subject matter:
1. A microprocessor, comprising:
a central processing unit;
at least one call stack structure;
a stack pointer structure;
an address bus;
a data bus; and
a hardware monitor configured to:
generate a plurality of protection codes;
insert the plurality of protection codes in the at least one
call stack structure or let the central processing unit insert the
plurality of protection codes in the at least one call stack
structure;
store addresses of the plurality of protection codes
inserted in the at least one call stack structure; and
generate an error signal in response to an attempt to
modify a first protection code of the plurality of protection
codes present in the at least one call stack structure.
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Application 13/543,673
References
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Shelton et al.
Cowan et al.
Fuente et al.
Borde et al.
Enbody et al.
Tilton et al.
U.S. Patent 6,035,380
US 2003/0182572 Al
US 2005/0027958 Al
US 2007/0089088 Al
US 2008/0140884 Al
US 2010/0017660 Al
Mar. 7, 2000
Sept. 25, 2003
Feb. 3, 2005
Apr. 19, 2007
June 12, 2008
Jan. 21, 2010
Conti EP 1,708,071 Al pub. Oct. 4, 2006
Tanenbaum, Andrew S. “1.4 Hardware, Software, and Multilevel
Machines.” Structured Computer Organization, 2d ed., Prentice-Hall,
Inc., 1984, pp. 10-12 (hereafter “Tanenbaum”).
Tamoff, David. “The Intel 8088 Architecture.” Introduction to
Microprocessors, East Tennessee State University, last modified Jan.
2003, faculty.etsu.edu/tamoff/ntes2150/uproc/arch8088.htm (hereafter
“Tamoff’).
Rejections2
Claims 1,5, and 12—14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Enbody, Tamoff, Tilton, and Tanenbaum. (Final
Act. 7-15.)
Claims 2—4, 8, 9, 15, and 16 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Enbody, Tamoff, Tilton, Tanenbaum, and
Cowan. (Final Act. 16—23.)
2 All rejections are under the provisions of 35 U.S.C. in effect prior to the
effective date of the Leahy-Smith America Invents Act of 2011. (Final Act.
2.)
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Application 13/543,673
Claim 2 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tamoff, Tilton, Tanenbaum, and Conti. (Final
Act. 23-24.)
Claims 6 and 7 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tamoff, Tilton, Tanenbaum, and Fuente. (Final
act. 24—26.)
Claims 10 and 11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tamoff, Tilton, Tanenbaum, Cowan, and Fuente.
(Final Act. 26—28.)
Claim 17 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tanenbaum, Tamoff, and Tilton. (Final Act. 28—
32.)
Claims 18 and 20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tanenbaum, Tamoff, Tilton, and Cowan. (Final
Act. 32-34.)
Claim 19 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Enbody, Tanenbaum, Tamoff, Tilton, Fuente, and
Shelton. (Final Act. 35—36.)
Claims 1—4, 8, and 9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Borde, Tamoff, and Tanenbaum. (Final Act. 37-41.)
Claims 6, 7, 10, and 11 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Borde, Tamoff, Tanenbaum, and Fuente. (Final
Act. 41^4.)
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Application 13/543,673
Issue3
Whether the Examiner erred in finding the combination of Enbody,
Tamoff, Tilton, and Tanenbaum teaches or suggests a “hardware monitor”
configured as recited in independent claim 1.
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments the Examiner has erred. We disagree with Appellants’
conclusions and we adopt as our own: (1) the findings and reasons set forth
by the Examiner in the action from which this appeal is taken (Final Act. 7—
36) and (2) the reasons set forth by the Examiner in the Examiner’s Answer
in response to Appellants’ Appeal Brief. (Ans. 2—14.) We concur with the
conclusions reached by the Examiner, and we highlight the following for
emphasis.4
The Examiner relies on Enbody in combination with Tamoff, Tilton,
and Tanenbaum as teaching or suggesting the limitations of claim 1. (Final
Act. 7—11.) We agree the Examiner’s findings are supported by the cited
teachings of the prior art references. In particular, the Examiner finds
Enbody teaches most of the limitations of claim 1, including a “central
processing unit,” a “call stack structure,” generating a “protection code[],”
“inserting the protection code in the at least one call stack structure,” and
3 As Appellants correctly note, the Examiner’s objections to certain claim
language, to the drawings, and to the Specification are not before us on
appeal. (App. Br. 10-11; see Final Act. 2-4; Adv. Action.)
4 Only those arguments made by Appellants have been considered in this
decision. Arguments Appellants did not make in the briefs have not been
considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv).
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“generating an error signal in response to an attempt to modify a protection
code present in the at least one call stack structure.” {Id. at 7.) The
Examiner finds, however, that “Enbody does not explicitly teach a stack
pointer structure and an address bus and a data bus,” and also does not
explicitly teach a “plurality of protection codes” and that “generation,
insertion, storing and generation of error signals is performed by a hardware
monitor.” {Id. at 7—8.) As for those limitations, the Examiner finds “Tamoff
teaches a stack pointer structure to point to the stack and address and data
buses.” {Id. at 8.) The Examiner also finds, “Tilton . . . teaches stacks . . .
and detecting stack overflow by detecting an attempt to modify a memory
space ... by monitoring the bus . . . and generating an error signal when a
write attempt to the code is attempted . . . .” {Id. at 9.) The Examiner
further finds the combination of Enbody, Tamoff, and Tilton would suggest
to the ordinarily skilled artisan a plurality of stacks, and that “[w]ith the
plurality of stacks, there would be a plurality of canary words [protection
codes],” and further that the addresses of the protection codes would be
“stored to be monitored on the bus.” {Id.)
Finally, although the Examiner finds the combination of Enbody,
Tilton, and Tamoff does not explicitly teach implementing the “protection
code” functionality in a “hardware monitor,” as recited in claim 1, the
Examiner finds, “Tannenbaum [sic] teaches that hardware and software are
logically equivalent and any operation that can be performed in software can
also be directly built into the hardware . . . .” {Id. at 10.) The Examiner
further finds:
One of ordinary skill in the art, with the teachings of
Enbody, Tamoff, Tilton and Tannenbaum before them, would
implement the generation, insertion, storing and generation of
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Application 13/543,673
error signals to be performed in hardware and this hardware
logic would be the hardware monitor. This would have been
obvious to a person of ordinary skill in the art to try the
hardware implementation for the generating, insertion, storing
and generation of error signals, as a person with ordinary skill
has good reason to pursue the known finite options within his or
her technical grasp.
{Id. at 10-11; see also Ans. 7—8.)
Appellants present several challenges on appeal, none of which we
find persuasive of Examiner error. First, Appellants take issue with the
Examiner’s reliance on multiple references, even though Appellants
acknowledge that “[rjeliance on a large number of references in a rejection
does not, without more, weigh against the obviousness of the claimed
invention.” (App. Br. 11 (emphasis added) (citing MPEP § 2145(V).)
Appellants also assert, based primarily on the number of references
combined, that the Examiner’s combination of references is based on
“hindsight.” (App. Br. 11—14.) We disagree that the Examiner has engaged
in improper hindsight reconstruction or has erred in combining the teachings
of the cited references. The Examiner has provided articulated reasoning for
combining all of the references that includes a rational underpinning (Final
Act. 8—11; Ans. 2—8), and Appellants do not substantively address the
Examiner’s findings in that regard.
Appellants also argue the Examiner errs in finding Tanenbaum
teaches or suggests that the protection code functionality as recited in claim
1 (and also in independent claims 12 and 17) could be implemented in
hardware to satisfy the claimed “hardware monitor” (claims 1 and 12) or
“monitoring circuit” (claim 17). (App. Br. 14—16.) Appellants argue in
particular that the “hardware monitor of claim 1 expressly provides
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hardware structure to generate and monitor protection codes, which cannot
be corrupted by a fraudulent alteration of the software program executed by
a CPU.” (Id. at 16.) Appellants’ argument emphasizing the advantage of
hardware over software misses the mark because it disregards the
Examiner’s finding that the ordinarily skilled artisan, in light of the
teachings of the combined references, would have been able to implement
the protection code functionality of claim 1 in hardware, as claimed. (See
Ans. 7—8.) As the Examiner notes:
[T]he combination [of prior art references] does not explicitly
teach that the functionality is implemented by hardware or by
software. The rejection relies on Tanenbaum to teach that
hardware and software are interchangeable, so that functionality
that can be implemented in software can be implemented in
hardware and vice versa. The combination with Tanenbaum
results in a hardware implementation of the functionality, thus a
hardware monitor.
(Id. ) We are not persuaded by Appellants’ arguments to the contrary, which
rely in part on the premise that “the Office has not provided even a single
reference that teaches a hardware monitor.” (App. Br. 16.) The test for
obviousness is not whether the claimed invention must be expressly
suggested in any one or all of the references. “Rather, the test is what the
combined teachings of the references would have suggested to those of
ordinary skill in the art.” In re Keller, 642 F.2d 413, 425 (CCPA 1981)
(citations omitted) (emphasis added). Thus, where, as here, the rejections
are based upon the teachings of a combination of references, “[n]on-
obviousness cannot be established by attacking references individually.” In
re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (citing Keller, 642
F.2d at 425). In addition, a reference “must be read, not in isolation, but for
what it fairly teaches in combination with the prior art as a whole.” Id.
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Appellants’ argument that the Examiner erred in construing the term
“hardware monitor” under 35 U.S.C. § 112(f) as a “means-plus-fimction”
term (App. Br. 17—18) is also not persuasive of Examiner error in the
rejection. In reviewing the Examiner’s finding that the claimed “hardware
monitor” is taught or suggested by the cited combination of references, we
are affording the term “hardware monitor” its broadest reasonable
interpretation in light of the specification as hardware configured to perform
the functions as recited in claim 1.
We are also not persuaded by Appellants’ additional arguments
challenging various aspects of each individual reference. (App. Br. 19—23.)
In particular, Appellants argue the Examiner’s findings regarding Enbody
are in error because Enbody “discusses only a buffer” and “[tjhere is no
teaching that Enbody’s buffer is a stack, and there is no teaching that
Enbody’s pointer is a stack pointer.” (App. Br. 20.) We disagree. As the
Examiner finds, “Enbody teaches a stack but does not explicitly teach a top
of stack pointer,” and relies on Enbody in combination with Tamoff, which
the Examiner finds “results in an explicit teaching of the address and the
data buses and the stack pointer, as required by the claim.” (Ans. 3—4.)
Appellants also argue the Examiner errs in finding the combination of
references teaches or suggests “storing] addresses of the plurality of
protection codes inserted in the at least one call stack structure.” (App. Br.
20-21.) Appellants’ arguments in this regard largely depend on challenging
each of the references individually which, as noted supra, is unpersuasive.
See Keller, 642 F.2d at 425. In addition, the Examiner finds:
Enbody teaches protecting a canary word (protection code) in a
stack by storing a secure bit (Fig. 3). The secure bit detects an
attempt to modify the canary word. Tilton teaches
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implementing a plurality of stacks. The combination with
Tilton results in implementing a plurality of stacks in the
processor of Enbody and Tarnoff. As a stack stores a canary
word, with a plurality of stacks each storing a canary word, the
combination would result in a plurality of protection codes
(canary words). Tilton teaches detecting an attempt to modify a
memory space by monitoring the bus. The combination with
Tilton results in detecting an attempt to modify the canary word
by monitoring the bus instead of storing a secure bit. As there
are multiple canaries, there are multiple addresses (of the
canary words) that have to be monitored on the bus. The
addresses to be monitored have to be stored so that they can be
monitored. The combination with Tanenbaum results in a
hardware monitor to implement the functionality.
(Ans. 4—5.) We agree these findings are supported by the teachings of the
cited references, and Appellants have not persuaded us these findings are in
error.
For the foregoing reasons, we are not persuaded of error in the
Examiner’s 35 U.S.C. § 103(a) rejection of independent claim 1, or of
independent claims 12 and 17, which are argued collectively with claim 1
(App. Br. 11—16, 19-23). We, therefore, sustain the rejection of independent
claims 1, 12, and 17 as unpatentable over the combination of Enbody,
Tarnoff, Tilton, and Tanenbaum. Appellants do not argue any of the
dependent claims individually. Therefore, we sustain the Examiner’s
obviousness rejections of dependent claims 5,13, and 14 over that
combination. We also sustain the Examiner’s rejections of dependent claims
2-4, 6—11, 15, 16, and 18—20 over the additionally cited prior art listed
above, as Appellants have not particularly pointed out errors in the
Examiner’s reasoning regarding the additional teachings of the further cited
art.
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The Examiner rejects independent claim 1, and dependent claims 1—4
and 6—11, under 35 U.S.C. § 103(a) over Borde as the primary reference
combined with Tamoff and Tanenbaum (and an additional reference, Fuente,
as to claims 6, 7, 10, and 11). (Final Act. 37-44.) As stated above, we
affirm the rejection of independent claim 1 as obvious over the combination
of Enbody, Tamoff, Tilton, and Tanenbaum (and the respective dependent
claims over that combination and others as stated above). Consequently, we
find it unnecessary to reach a decision about the cumulative rejections under
35 U.S.C. § 103(a) over the combination of Borde in view of Tamoff and
Tanenbaum (and Fuente). See 37 C.F.R. § 41.50(a)(1) (“The affirmance of
the rejection of a claim on any of the grounds specified constitutes a general
affirmance of the decision of the examiner on that claim . . . .”).
DECISION
For the above reasons, the Examiner’s rejection of claims 1—20 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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