Ex Parte Goto et al

Patent Trial and Appeal Board

May 5, 2017

12552027 (P.T.A.B. May. 5, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/552,027 09/01/2009 Akio Goto MP2876/ 13361-0221001 3760
26200 7590 05/09/2017
FISH & RICHARDSON P.C. (MARVELL)
P.0 BOX 1022
MINNEAPOLIS, MN 55440-1022
EXAMINER
LI, SIDNEY
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
05/09/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PATDOCTC@fr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex Parte AKIO GOTO, CHI KONG LEE, and MASAYUKIURABE
Appeal 2017-000721
Application 12/552,027
Technology Center 2100
Before CAROLYN A. THOMAS, BETH Z. SHAW, and
NABEEL KHAN, Administrative Patent Judges.
SHAW, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1, 2, 9, 16, 20—22, and 26—29
(“pending claims”), which represent all the pending claims. Notice of
Appeal. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
INVENTION
Appellants’ invention is directed to programming data into a multi­
plane memory device. See Spec. 1 5.
Appeal 2017-000721
Application 12/552,027
Claim 1 is illustrative and is reproduced below:
1. A method comprising:
receiving a first subset of first data and a first subset of
second data;
storing the first subset of the first data in a first page
buffer and storing the first subset of the second data in a second
page buffer, wherein the first page buffer and the second page
buffer have a size equivalent to one page of a memory plane;
programming the stored first subset of the first data into a
first page associated with a first memory plane of a multi-plane
memory device;
programming the stored first subset of the second data
into a second page associated with the first memory plane in
parallel with programming the stored first subset of the first
data;
while programming the stored first subset of the first data
into the first page associated with the first memory plane of the
multi-plane memory device, receiving a second subset of the
first data and storing the second subset of the first data in the
first page buffer;
while programming the stored first subset of the second
data into the second page associated with the first memory
plane, receiving a second subset of the second data and storing
the second subset of the second data in the second page buffer;
programming the stored second subset of the first data
into a first page associated with a second memory plane of the
multi-plane memory device after programming the stored first
subset of the second data into the second page associated with
the first memory plane; and
programming the stored second subset of the second data
into a second page associated with the second memory plane.
REJECTION
The Examiner rejected claims 1, 2, 9, 16, 20-22, and 26—29 under 35
U.S.C. § 112, first paragraph, as failing to comply with the written
description requirement. Final Act. 3—5.
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Application 12/552,027
The Examiner rejected claims 1, 2, 9, 16, 20—22, and 26—29 under 35
U.S.C. § 112, second paragraph, as being indefinite. Final Act. 5—7.
The Examiner rejected claims 1,21, and 27 under 35 U.S.C. § 103(a)
as being unpatentable over Park (US 2008/0101120 Al, pub. May 1, 2008)
and Lee (US 2008/0055993 Al, pub. Mar. 6, 2008). Final Act. 7—13.
The Examiner rejected claims 2, 9, 16, 20, 22, 26, 28, 29 under
35 U.S.C. § 103(a) as being unpatentable over Park, Lee, and Dortu (US
2003/0191912 Al, pub. Oct. 9, 2003). Final Act. 13-16.
ANALYSIS
We have reviewed Appellants’ arguments in the Briefs, the
Examiner’s rejection, and the Examiner’s response to the Appellants’
arguments. We concur with Appellants’ conclusion that the Examiner erred
in rejecting the pending claims under 35 U.S.C. § 112, first paragraph and 35
U.S.C. § 112, second paragraph. We also concur with Appellants’
conclusion that the Examiner erred in finding that the combination of Park
and Lee teaches
while programming the stored first subset of the first data into
the first page associated with the first memory plane of the
multi-plane memory device, receiving a second subset of the
first data and storing the second subset of the first data in the
first page buffer; while programming the stored first subset of
the second data into the second page associated with the first
memory plane, receiving a second subset of the second data and
storing the second subset of the second data in the second page
buffer,
as recited in claim 1.
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Appeal 2017-000721
Application 12/552,027
Written Description
The Examiner rejected the claims as lacking written description
support (“The specification does not provide sufficient support for
programming the second memory plane’s pages at exactly the same time”
(Final Act. 3); “The specification clearly does not support while
programming the stored first subset, receiving a second subset of the first
data in to the buffer” (id. at 4)). We concur with Appellants’ conclusion that
the Examiner erred in rejecting the pending claims under 35U.S.C. § 112,
first paragraph. “[T]he test for sufficiency of support... is whether the
disclosure of the application relied upon ‘reasonably conveys to the artisan
that the inventor had possession at that time of the later claimed subject
matter.’” Ralston Purina Co. v. Far-Mar-Co., Inc., 772 F.2d 1570, 1575
(Fed. Cir. 1985) (quoting In re Kaslow, 707 F.2d 1366, 1375 (Fed. Cir.
1983)).
First, as Appellants point out, the original Specification provides
support for the claims and explains parallel operations. Spec. 138,1104,
Fig. 4A. Contrary to Appellants’ broad description of parallel operations,
the Examiner is requiring the claimed “in parallel” to be “exactly at the same
time” (Final Act. 3). We therefore agree with Appellants that the
Specification shows support for the claimed “programming the stored first
subset of the second data into a second page associated with the first
memory plane in parallel with programming the stored first subset of the
first data.” We also highlight that original claim 1 included an “in parallel”
recitation and the original claims provide literal support for themselves. See
In re Anderson, 471 F.2d 1237, 1238-39 (CCPA 1973) (unamended original
claim is a part of the original disclosure).
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Appeal 2017-000721
Application 12/552,027
Moreover, we agree with Appellants that the original Specification, in
particular in at least paragraphs 5, 41, and 100-103, supports
while programming the stored first subset of the first data into
the first page associated with the first memory plane of the
multi-plane memory device, receiving a second subset of the
first data and storing the second subset of the first data in the
first page buffer [and] while programming the stored first
subset of the second data into the second page associated with
the first memory plane, receiving a second subset of the second
data and storing the second subset of the second data in the
second page buffer.
App. Br. 9-10.
The Examiner acknowledges that the Specification describes data to
be programmed into pages associated with a succeeding plane “can be read
into and cached in one or more page buffers,” but finds this disclosure is
insufficient to teach the data to be programmed into the succeeding plane is
cached in “the same page buffer.” Final Act. 4—5; Ans. 18—19 (citing Spec.
11 5, 41). However, we agree with Appellants that paragraph 5 of the
Specification explains that “[w]hile the data transfer program operation is in
progress, data to be programmed into a succeeding plane (e.g., plane ‘1’) can
be read into and cached in one or more page buffers,” (emphasis added), and
Figure 4 A illustrates that Plane 0 and Plane 1 share the same set of page
buffers. App. Br. 10.
For these reasons, we do not sustain the rejection of the pending
claims under 35U.S.C. § 112, first paragraph.
Indefiniteness
We concur with Appellants’ conclusion that the Examiner erred in
rejecting the pending claims under 35 U.S.C. § 112, second paragraph, as
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Appeal 2017-000721
Application 12/552,027
being indefinite. The Examiner rejected the pending claims because the
Examiner finds it unclear if Appellants’ programming is occurring at exactly
the same time. Final Act. 6. We agree with Appellants (App. Br. 6—7, 11)
that the Specification, for example paragraphs 38 and 104, makes clear that
“parallel” as claimed does not require the respective program operations to
start at exactly the same time. In particular, we agree the claims do not
require “programming the second memory plane’s pages at exactly the same
time.” App. Br. 5. Rather, claim 1 recites “programming the stored first
subset of the second data into a second page associated with the first
memory plane in parallel with programming the stored first subset of the
first data” (emphasis added).
The Examiner interprets “in parallel with” as “at exactly the same
time,” relying on a dictionary definition. Final Act 3. However, we agree
with Appellants that “the best source for determining the meaning of a claim
term is the specification.” M.P.E.P. § 2111.01(1) and 2173.01(1). “If
extrinsic reference sources, such as dictionaries, evidence more than one
definition for the term, the intrinsic record must be consulted to identify
which of the different possible definitions is most consistent with applicant’s
use of the terms.” Ferguson Beauregard/Logic Controls v. Mega Systems,
350 F.3d 1327, 1338, 69 USPQ2d 1001, 1009 (Fed. Cir. 2003).
We agree with Appellants that based on the Specification, one skilled
in the art would recognize that the programming of the data to the different
pages can occur in parallel such that both the first page and the second page
of the memory plane is programmed after the PROGRAM operation
associated with programming the second page is initialized. App. Br. 7.
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Application 12/552,027
(citing Spec. Fig. 4B.)
For these reasons, we do not sustain the Examiner’s rejection of the
pending claims under 35 U.S.C. § 112, second paragraph.
Section 103 Rejection
We agree with Appellants that the cited portions of Lee do not teach
or suggest receiving and storing data in a page buffer while programming
data previously stored in the same page buffer. App. Br. 13. The Examiner
appears to acknowledge that the cited portion of Lee (i.e., Lee 121) does not
teach this element as claimed. Ans. 20—21. Instead, in the Answer, the
Examiner points to portions of Appellants’ Specification (Ans. 20—21), but
the Examiner does not explain the relevance of these portions of Appellants’
Specification to the analysis of how Lee teaches the claimed elements.
Thus, we are persuaded by Appellants that the Examiner has not
shown Park and Lee, taken alone or in proper combination, teaches or
suggests
while programming the stored first subset of the first data into
the first page associated with the first memory plane of the
multi-plane memory device, receiving a second subset of the
first data and storing the second subset of the first data in the
first page buffer; while programming the stored first subset of
the second data into the second page associated with the first
memory plane, receiving a second subset of the second data and
storing the second subset of the second data in the second page
buffer,
as recited in claim 1, and as similarly recited in independent claims 21 and
27. The Examiner has not shown that Dortu makes up for the above-noted
deficiencies.
Accordingly, we do not sustain the Examiner’s rejection of claims 1,
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Appeal 2017-000721
Application 12/552,027
2, 9, 16, 20-22, and 26-29 under 35 U.S.C. § 103(a).
DECISION
The decision of the Examiner to reject claims 1, 2, 9, 16, 20—22, and
26—29 is reversed.
REVERSED
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