Ex Parte Gorman et al

Patent Trial and Appeal Board

Jan 31, 2017

13786572 (P.T.A.B. Jan. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/786,572 03/06/2013 Kevin W. Gorman BUR920120163US1 9913
45094 7590 02/02/2017
HOFFMAN WARNTOK T T C EXAMINER
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VALLECILLO, KYLE
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NOTIFICATION DATE DELIVERY MODE
02/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KEVIN W. GORMAN, DEEPAK I. HANAGANDI,
KRISHNENDU MONDAL, and MICHAEL R. OUELLETTE1
Appeal 2016-003434
Application 13/786,572
Technology Center 2100
Before MICHAEL J. STRAUSS, DANIEL N. FISHMAN, and
JAMES W. DEJMEK, Administrative Patent Judges.
FISHMAN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1,3,4, 7—9, and 12—16. Claims 2, 5, 6, 10, 11, and 17—20 have been
canceled. Final Act. 2. We have jurisdiction over the pending claims under
35 U.S.C. § 6(b).
We affirm-in-part.
1 Appellants identify International Business Machines Corporation as the
real party in interest. App. Br. 1.
Appeal 2016-003434
Application 13/786,572
THE INVENTION
Appellants’ invention is directed to “reducing the test time of a built-
in-self-test (BIST) for a memory of an integrated circuit (IC) chip.”
Spec. 11.
Independent claims 1 and 7, reproduced below, are exemplary:
1. A built-in-self-test (BIST) architecture for reducing BIST
test time of a memory for an integrated circuit (IC) chip, the
architecture comprising:
a latch for receiving a burst of data from a memory;
a first compression stage for receiving the burst of data and
for compressing the burst of data into a plurality of AND and OR
latches, wherein the first compression stage includes a plurality
of AND gates, each AND gate having an output stored in a
respective one of the plurality of AND latches, each AND latch
having an output, and a plurality of OR gates, each OR gate
having an output stored in a respective one of the plurality of OR
latches, each OR latch having an output;
a second compression stage for comparing the compressed
bursts of data with expected data; and
a logic gate for determining whether there is a fail in the
burst of data;
wherein the second compression stage includes:
a plurality of multiplexors for receiving the outputs
of the plurality of AND latches and the outputs of the plurality
of OR latches; and
wherein the expected data is a selection signal for
each of the plurality of multiplexors.
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Appeal 2016-003434
Application 13/786,572
7. A method of reducing test time for a built-in-self-test
(BIST) architecture, the method comprising:
performing a first read of the BIST, wherein the
performing includes:
receiving a burst of data from a memory at a pair of
latches;
compressing the burst of data in a first compression
stage; and
comparing the compressed burst of data with
expected data;
determining whether there is fail in the burst of data; and
in response to determining a fail in the burst of data,
performing a second read of the BIST for the received burst of
data.
THE REJECTIONS
Claims 1,3, and 4 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Cheng et al. (US 2008/0294953 Al; Nov. 27, 2008)
(“Cheng ’953”). Final Act. 6-10.
Claims 7—9 and 12—16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Cheng ’953 and Cheng et al. (US 2009/0254786
Al; Oct. 8, 2009) (“Cheng ’786”). Final Act. 11-17.
ANALYSIS
Only those arguments actually made by Appellants have been
considered in this Decision. Arguments that Appellants did not make in the
Briefs are waived. See 37 C.F.R. § 41.37(c)(l)(iv).
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner erred. App. Br. 4—7; Reply Br. 2—7. We find
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Appeal 2016-003434
Application 13/786,572
Appellants’ arguments in connection with the rejection of claims 1,3,4, and
12 persuasive of Examiner error. However, we are not persuaded by
Appellants’ contentions of Examiner error regarding claims 7—9 and 13—16.
Accordingly, we adopt as our own the Examiner’s findings and reasons set
forth Final Action and the Answer solely in connection with claims 7—9 and
13—16. Final Act. 2—17; Ans. 3—21. We highlight and address specific
arguments and findings for emphasis as follows.
Claims 1, 3, and 4
The Examiner finds Cheng ’953 discloses scan chains and asserts the
scan chains, as described in paragraph 4 of Cheng ’953, are latches.
Final Act. 8 (citing Cheng ’953 1102, Fig. 17). The Examiner further finds
Cheng ’953 discloses a compactor that “comprises a network of
combinational logic (for example, XOR or XNOR gates).” Final Act. 3, 6—8
(quoting Cheng ’953 55); see also Ans. 7, 8. The Examiner asserts “it is
well known in the art that ‘XOR or XNOR gates’ may be constructed using
a combination of OR and AND gates” (Final Act. 3, 8; see also Ans. 8) and,
thus, apparently asserts the specific claimed structure of AND and OR gates
is obvious over the mere mention in Cheng ’953 of XOR gates, XNOR
gates, and latches.
Appellants contend the Examiner failed to establish a prima facie case
of obviousness in rejecting claim 1 by failing to show Cheng ’953 teaches or
suggests “a plurality of AND gates, each AND gate having an output stored
in a respective one of the plurality of AND latches” and “a plurality of OR
gates, each OR gate having an output stored in a respective one of the
plurality of OR latches,” as recited in claim 1. App. Br. 4—6.
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Appeal 2016-003434
Application 13/786,572
We are persuaded the Examiner erred. Appellants’ claimed
architecture recites a very specific structure comprising a plurality of AND
gates and OR gates. See, e.g., claim 1. Further, the output of each AND
gate is stored in an AND latch, each AND latch having an output, the output
of each OR gate is stored in an OR latch, each OR latch having an output.
See, e.g., claim 1.
We agree with Appellants that Cheng ’953 does not expressly teach
the claimed architecture. Although we agree with the Examiner that it
would have been trivial for one of ordinary skill in the art to have
implemented an architecture of XOR and XNOR gates using a plurality of
AND, OR, and NOT gates (see Final Act. 3, 8; see also Ans. 8), the
Examiner has not provided sufficient evidence or explanation that the output
of each AND gate and each OR gate would necessarily be stored in a
corresponding AND latch or OR latch, respectively, if the architecture
disclosed in Cheng ’953 were implemented using a plurality of AND and
OR gates.
For the reasons discussed supra, and on the record before us, we are
constrained to reverse the Examiner’s rejection of independent claim 1.
Additionally, we do not sustain the Examiner’s rejection of claims 3 and 4,
which depend therefrom.
Claims 7—9
The Examiner finds Cheng ’953 teaches performing a first read of a
BIST. Final Act. 11,13 (citing Cheng ’953 Tflf 5, 102, Fig. 17). Further, the
Examiner relies on Cheng ’953 to teach determining whether there is a
failure in a received and compressed burst of data. Final Act. 11—13
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Application 13/786,572
(citing Cheng ’953 Tflf 4, 8, 9, 55, 102). The Examiner relies on Cheng ’786
to teach, in response to determining a failure in a compressed mode, a
second read is performed by retesting reconfigured designs in an
uncompressed mode. Final Act. 13 (citing Cheng ’7861 5). Thus, the
Examiner asserts combination of Cheng ’953 and Cheng ’786 teaches or
suggests in response to determining a fail in a burst of data, performing a
second read of a BIST for a received burst of data.
Appellants contend the Examiner erred in finding the combination of
Cheng ’953 and Cheng ’786 teaches or suggests “performing a first read of
the BIST” and “in response to determining a fail in the burst of data,
performing a second read of the BIST for the received burst of data,” as
recited in claim 7. App. Br. 7; Reply Br. 6.
We are unpersuaded of Examiner error. Our rules require more
substantive arguments in an appeal brief than a mere recitation of the claim
elements and a naked assertion that the corresponding elements were not
found in the prior art. 37 C.F.R. § 41.37(c)(l)(iv); see also In re
Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011). Appellants’ argument
amounts to nothing more than a general assertion that the disputed claim
limitations are absent from the prior art. Thus, in the absence of sufficient
persuasive evidence or argument to rebut the Examiner’s findings,
Appellants’ arguments are unpersuasive of Examiner error and we sustain
the rejection of claim 7 as well as claims 8 and 9 dependent therefrom and
not separately argued.
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Appeal 2016-003434
Application 13/786,572
Claims 12 16
Claims 12—16 depend from claim 7 and generally recite additional
method limitations that relate to combinational logic structures in which the
method steps operate. Specifically, claim 12 depends from claim 7 and
further recites, “wherein compressing the burst of data in the first
compression stage includes sending the burst of data to a plurality of AND
gates and a plurality of OR gates.” Claims 13—16 depend from claim 12 and
recite further method limitations relating to still other structural limitations.
The Examiner relies on paragraphs 5, 55, 101, and 102 of Cheng ’953
as disclosing the gate, latch, and multiplexor structures recited in claims 12—
16. Final Act. 15—16.
As above, regarding claim 7, Appellants contend Cheng ’953 “fails to
teach or suggest, inter alia, the configuration of AND gates, OR gates, AND
latches, OR latches, and multiplexors presented in claims 12—16, as well as
the claimed ‘expected data is a selection signal’ of claim 16.” App. Br. 7.
As discussed with respect to claim 1, the Examiner finds, and we
agree, it would have been obvious to one of ordinary skill in the art to
implement the compression stage architecture of Cheng ’953 comprising
XOR and XNOR gates using a plurality of AND and OR gates as is well-
known to those of ordinary skill in the art. The claimed structure in which
the step of claim 12 is performed merely recites a compression stage
comprising a plurality of AND gates and a plurality of OR gates. Thus, we
are not persuaded the Examiner erred in rejecting claim 12. The simple
structural recitation of method claim 12 (a plurality of AND and OR gates)
is taught or at least suggested by compactor 220 of Cheng ’953 that typically
comprises XOR and XNOR gates. Final Act. 15.
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Appeal 2016-003434
Application 13/786,572
Claims 13—16 depend (directly or indirectly) from claim 12, each
reciting additional structural aspects of the claimed method. As discussed
supra with respect to claim 1, the Examiner has not provided sufficient
evidence or explanation that AND gates and OR gates have outputs coupled
to corresponding latches, which, in turn, have outputs coupled to
multiplexors, etc. Although such constructs may have been trivial and well-
known to the ordinarily skilled artisan at the time of the invention, the
Examiner has not presented sufficient support for such a conclusion.
For the above reasons, we sustain the rejection of claim 12 but, on the
record before, we do not sustain the rejection of claims 13—16.
DECISION
We reverse the Examiner’s decision to reject claims 1, 3, 4, and 13—
16.
We affirm the Examiner’s decision to reject claims 7—9 and 12.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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