Ex Parte Ganitzer et al

Patent Trial and Appeal Board

Apr 28, 2014

11439749 (P.T.A.B. Apr. 28, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte PAUL GANITZER and STEFAN WOEHLERT
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Appeal 2012-002862
Application 11/439,749
Technology Center 2800
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Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.

TIMM, Administrative Patent Judge.

DECISION ON APPEAL

Appellants seek review of the Examiner’s decision to reject claims 1-
5, 21, and 22 under 35 U.S.C. § 103(a) as obvious over the combination of
Lee,1 Lau,2 and Eldridge.3 We have jurisdiction under 35 U.S.C. §§ 6(b) and
134.

1 Lee et al., A New Bonding Technology Using Gold and Tin Multilayer
Composite Structures, 14 IEEE Transactions on Components, Hybrids, and
Manufacturing Technology 407-412 (1991).
2 Lau et al., US 6,294,402 B1, patented Sept. 25, 2001.
3 Eldridge et al., US 5,884,398, patented Mar. 23, 1999.
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Application 11/439,749

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For the reasons given by the Examiner in the Answer, we AFFIRM.
We add the following primarily for emphasis.

The claims are directed to a silicon wafer (see, e.g., claim 1) or silicon
chip (see, e.g., claim 3) with a solderable coating on its rear-side.
Appellants argue the claims as a group (Br. 10), therefore, we select claim 1
as representative. Claim 1 reads:
1. A silicon wafer comprising:
a wafer top side with integrated circuits; and
a wafer rear side with an exposed solderable coating
applied thereto, the exposed solderable coating comprising a
gold/tin solder material, the rear side coating being free of
silver constituents in the immediate vicinity of the solderable
coating, and the gold/tin solder material being arranged on an
adapted gold coating, the volume of gold in the adapted gold
coating, together with the volume of gold in the solder material
in relation to the volume of tin in the solder material
corresponding to the eutectic melt system of gold and tin in
thermodynamic equilibrium.
(Claims App’x at Br. 15.)
As pointed out by Appellants, their Figure 3 illustrates a coated silicon
wafer of the claimed structure (Br. 11). Figure 3 is reproduced below:
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Application 11/439,749

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Figure 3 is a diagrammatic cross-section through a silicon wafer coated with
a rear-side coating 4.3

In addition to the solderable coating comprising gold/tin solder
material and adapted gold coating 7.3 recited in claim 1 (collectively 6.3 in
Fig. 3), the rear-side coating 4.3 includes an aluminum contact layer 9.3, and
a diffusion barrier layer 10.3 between the silicon wafer 2 and the solderable
coating 6.3 (id.; see also Spec. 11-12).
The Specification describes the coating regime as an improvement
over a prior art structure, which according to EP 0 072 273, has on the rear-
side of the silicon wafer a bonding metal coating 9.1 of predominately
chromium with a residual silver content followed by a gold/tin solder layer
6.1 (Spec. 2:8-16; Fig. 1). Appellants’ coating regime eliminates silver from
the immediate vicinity of the gold/tin solder material and instead inserts a
layer of gold (Spec. 6:3-16).
There is no dispute that Lee teaches gold/tin layers meeting the
requirements of the solderable coating material of claim 1 (Br. 11-12; see
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Application 11/439,749

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also Lee, Fig. 2 layers no. 2/3/4). As shown in Lee’s Figure 2, a device die
is coated with chromium (Cr) or titanium (Ti), then gold (Au), tin (Sn), and
gold (Au) to form a (Cr or Ti)-Au-Sn-Au composite (referred to as a Cr-Au-
Sn-Au composite in Lee (§ III, ¶ 1)). Lee does not specify the identity of the
material of the device die, and only exemplifies depositing the (Cr or Ti)-
Au-Sn-Au layer structure onto a Gallium Arsenide (GaAs) wafer (Lee, §
IV). The dispute is whether one of ordinary skill in the art would have
found it obvious to apply the layers of Lee onto a silicon wafer. We
determine that a preponderance of the Examiner supports the Examiner’s
conclusion that it would have been obvious to deposit the (Cr or Ti)-Au-Sn-
Au layers of Lee onto a silicon wafer.
The Examiner relies upon Eldridge as evidence of the equivalence of
silicon wafers and gallium-arsenide wafers (Ans. 5-6, citing Eldridge, col.
16, ll. 17-21). But Appellants point out that the adhesion performance of the
solderable layer depends on the properties of the substrate onto which it is
mounted (Br. 11-12). We agree with Appellants that the adhesion
performance is material dependent, but Lee includes a bonding layer, just as
Appellants do. Appellants’ own Specification indicates that one of Lee’s
suggested bonding layers, the chromium layer, was a known bonding layer
for use between silicon wafers and gold/tin solder material (Spec. 1-2; Fig.
1). Therefore, we cannot say that Appellants have identified a reversible
error in the Examiner’s rejection.
Appellants contend that combining the teachings of Lee, Lau, and
Eldridge would likely result in a non-functional device because
Eldridge teaches techniques for exercising semiconductor
devices prior to their packaging and to temporary, pressure
connections between electronic components. Column 7, lines
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57 to 60 of Eldridge teaches that soldering to effect the
interconnection to a terminal of an electronic component is
generally not preferred. Lee and Lau, on the other hand, both
teach a method of soldering an integrated circuit chip to a
substrate.
(Br. 12.) But none of these teachings negate the evidence within the record
indicating that bonding a silicon wafer to a solderable coating by way of a
bonding layer, such as chromium bonding layer, was known in the art.
A preponderance of the evidence supports the Examiner’s conclusion
of obviousness.
We sustain the Examiner’s rejection.

DECISION
The Examiner’s decision is affirmed.

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).

AFFIRMED

cdc